ISL62883_14 Datasheet, PDF (4/37 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs

ISL62883, ISL62883B
VSSP2
Current return path for the Phase-2 converter low-side MOSFET
gate driver. Connect the VSSP2 pin to the source of the Phase-2
low-side MOSFET through a low impedance path, preferably in
parallel with the trace connecting the LGATE2 pin to the gate of
the Phase-2 low-side MOSFET.
PHASE2
Current return path for the Phase-2 high-side MOSFET gate driver.
Connect the PHASE2 pin to the node consisting of the high-side
MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase-2.
UGATE2
Output of the Phase-2 high-side MOSFET gate driver. Connect the
UGATE2 pin to the gate of the Phase-2 high-side MOSFET.
BOOT2
Connect an MLCC capacitor across the BOOT2 and the PHASE2
pins. The boot capacitor is charged through an internal boot
diode connected from the VCCP pin to the BOOT2 pin, each time
the PHASE2 pin drops below VCCP minus the voltage dropped
across the internal boot diode.
VID0, VID1, VID2, VID3, VID4, VID5, VID6
VID input with VID0 = LSB and VID6 = MSB.
VR_ON
Voltage regulator enable input. A high level logic signal on this
pin enables the regulator.
DPRSLPVR
Deeper sleep enable signal. A high level logic signal on this pin
indicates that the microprocessor is in deeper sleep mode.
CLK_EN#
Open drain output to enable system PLL clock. It goes low 13
switching cycles after V_core is within 10% of V_boot.
NC
No Connect.
BOTTOM (on ISL62883B)
The bottom pad of ISL62883B is electrically connected to the
GND pin inside the IC.
4
FN6891.4
June 21, 2011