ISL62883_14 Datasheet, PDF (15/37 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs

ISL62883, ISL62883B
Differential Sensing
Figure 9 also shows the differential voltage sensing scheme.
VCC_SENSE and VSS_SENSE are the remote voltage sensing signals
from the processor die. A unity gain differential amplifier senses the
VSS_SENSE voltage and add it to the DAC output. The error amplifier
regulates the inverting and the non-inverting input voltages to be
equal as shown in Equation 3:
VCC_S
E
NS
E
+
V
d
r
o
op
=
V_DAC + VSS_SENSE
(EQ. 3)
Rewriting Equation 3 and substitution of Equation 2 gives:
VCC_SENSE – VSS_SENSE = V_DAC – R_droop × I_droop
(EQ. 4)
Equation 4 is the exact equation required for load line
implementation.
The VCC_SENSE and VSS_SENSE signals come from the processor
die. The feedback will be open circuit in the absence of the
processor. As shown in Figure 9, it is recommended to add a
“catch” resistor to feed the VR local output voltage back to the
compensator, and add another “catch” resistor to connect the VR
local output ground to the RTN pin. These resistors, typically
10Ω~100Ω, will provide voltage feedback if the system is
powered up without a processor installed.
Phase Current Balancing
ISEN3
INTERNAL
TO IC
ISEN2
Phase3
Rs
Cs
Phase2
Rs
Cs
ISEN1
Phase1
Rs
Cs
L3
Rdcr3 _Rpcb3
IL3
L2
Rdcr2 _Rpcb2
Vo
IL2
L1
Rdcr1 _Rpcb1
IL1
FIGURE 10. CURRENT BALANCING CIRCUIT
The ISL62883 monitors individual phase average current by
monitoring the ISEN1, ISEN2, and ISEN3 voltages. Figure 10
shows the current balancing circuit recommended for ISL62883.
Each phase node voltage is averaged by a low-pass filter
consisting of R_s and C_s, and presented to the corresponding ISEN
pin. R_s should be routed to inductor phase-node pad in order to
eliminate the effect of phase node parasitic PCB DCR.
Equations 5 thru 7 give the ISEN pin voltages:
V_ISEN1 = (R_dcr1 + R_pcb1) × I_L1
(EQ. 5)
V_ISEN2 = (R_dcr2 + R_pcb2) × I_L2
(EQ. 6)
V_ISEN3 = (R_dcr3 + R_pcb3) × I_L3
(EQ. 7)
where R_dcr1, R_dcr2 and R_dcr3 are inductor DCR; R_pcb1, R_pcb2
and R_pcb3 are parasitic PCB DCR between the inductor output
side pad and the output voltage rail; and I_L1, I_L2 and I_L3 are
inductor average currents.
The ISL62883 will adjust the phase pulse-width relative to the
other phases to make V_ISEN1 = V_ISEN2 = V_ISEN3, thus to achieve
I_L1 = I_L2 = I_L3, when there are R_dcr1 = R_dcr2 = R_dcr3 and
R_pcb1 = R_pcb2 = R_pcb3.
Using same components for L1, L2 and L3 will provide a good
match of R_dcr1, R_dcr2 and R_dcr3. Board layout will determine
R_pcb1, R_pcb2 and R_pcb3. It is recommended to have symmetrical
layout for the power delivery path between each inductor and the
output voltage rail, such that R_pcb1 = R_pcb2 = R_pcb3.
ISEN3
INTERNAL
TO IC
ISEN2
ISEN1
V3p
Phase3
Rs
Rs
Cs
Rs
V2p
Phase2
Rs
Cs ^Rs
Rs
V1p
Phase1
Rs
Rs
Cs
Rs
L3 Rdcr3 _Rpcb3
IL3 _V3n
L2 Rdcr2 _{Rpcb2 Vo}
IL2 _V2n
L1 Rdcr1 _Rpcb1
IL1 _V1n
FIGURE 11. DIFFERENTIAL-SENSING CURRENT BALANCING
CIRCUIT
Sometimes, it is difficult to implement symmetrical layout. For
the circuit shown in Figure 10, asymmetric layout causes
different R_pcb1, R_pcb2 and R_pcb3 thus current imbalance.
Figure 11 shows a differential-sensing current balancing circuit
recommended for ISL62883. The current sensing traces should
be routed to the inductor pads so they only pick up the inductor
DCR voltage. Each ISEN pin sees the average voltage of three
sources: its own phase inductor phase-node pad, and the other
two phases inductor output side pads. Equations 8 thru 10 give
the ISEN pin voltages:
V_ISEN1 = V_1p + V_2n + V_3n
(EQ. 8)
V_ISEN2 = V_1n + V_2p + V_3n
(EQ. 9)
V_ISEN3 = V_1n + V_2n + V_3p
(EQ. 10)
The ISL62883 will make V_ISEN1 = V_ISEN2 = V_ISEN3 as in:
V_1p + V_2n + V_3n = V_1n + V_2p + V_3n
(EQ. 11)
V_1n + V_2p + V_3n = V_1n + V_2n + V_3p
(EQ. 12)
Rewriting Equation 11 gives:
V_1p – V_1n = V_2p – V_2n
(EQ. 13)
and rewriting Equation 12 gives:
V_2p – V_2n = V_3p – V_3n
(EQ. 14)
Combining Equations 13 and 14 gives:
V_1p – V_1n = V_2p – V_2n = V_3p – V_3n
(EQ. 15)
Therefore:
R_dcr1 × I_L1 = R_dcr2 × I_L2 = R_dcr3 × I_L3
(EQ. 16)
15
FN6891.4
June 21, 2011