ISL6251_06 Datasheet, PDF (4/20 Pages) Intersil Corporation – Low Cost Multi-Chemistry Battery Charger Controller

ISL6251, ISL6251A
Electrical Specifications
DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = 1.5V, ACLIM = VREF, VADJ = Floating,
EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, C_VDD = 1µF, I_VDD = 0mA, T_A = -10°C to +100°C,
T_J ≤ 125°C, unless otherwise noted. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OSCILLATOR
Frequency
245
300
355
kHz
PWM Ramp Voltage (peak-peak)
CSIP = 18V
1.6
V
CSIP = 11V
1
V
SYNCHRONOUS BUCK REGULATOR
Maximum Duty Cycle
97
99
99.6
%
UGATE Pull-Up Resistance
BOOT-PHASE = 5V, 500mA source current
1.8
3.0
Ω
UGATE Source Current
BOOT-PHASE = 5V, BOOT-UGATE = 2.5V
1.0
A
UGATE Pull-DOWN Resistance
BOOT-PHASE = 5V, 500mA sink current
1.0
1.8
Ω
UGATE Sink Current
BOOT-PHASE = 5V, UGATE-PHASE = 2.5V
1.8
A
LGATE Pull-UP Resistance
VDDP-PGND = 5V, 500mA source current
1.8
3.0
Ω
LGATE Source Current
VDDP-PGND = 5V, VDDP-LGATE = 2.5V
1.0
A
LGATE Pull-DOWN Resistance
VDDP-PGND = 5V, 500mA sink current
1.0
1.8
Ω
LGATE Sink Current
VDDP-PGND = 5V, LGATE = 2.5V
1.8
A
CHARGING CURRENT SENSING AMPLIFIER
Input Common-Mode Range
0
18
V
Input Offset Voltage
Guaranteed by design
-2.5
0
2.5
mV
Input Bias Current at CSOP
0 < CSOP < 18V
0.25
2
µA
Input Bias Current at CSON
0 < CSON < 18V
75
100
µA
CHLIM Input Voltage Range
0
3.6
V
CSOP to CSON Full-Scale Current
Sense Voltage
ISL6251: CHLIM = 3.3V
ISL6251A, CHLIM = 3.3V
157
165
173
mV
160
165
170
mV
ISL6251: CHLIM = 2.0V
95
100
105
mV
ISL6251A: CHLIM = 2.0V
97
100
103
mV
ISL6251: CHLIM = 0.2V
5.0
10
15.0
mV
ISL6251A: CHLIM = 0.2V
7.5
10
12.5
mV
CHLIM Input Bias Current
CHLIM = GND or 3.3V, DCIN = 0V
-1
1
µA
CHLIM Power-Down Mode Threshold CHLIM rising
Voltage
80
88
95
mV
CHLIM Power-Down Mode Hysteresis
Voltage
15
25
40
mV
ADAPTER CURRENT SENSING AMPLIFIER
Input Common-Mode Range
7
25
V
Input Offset Voltage
Guaranteed by design
-2
2
mV
Input Bias Current at CSIP and CSIN CSIP = CSIN = 25V
Combined
100
130
µA
Input Bias Current at CSIN
0 < CSIN < DCIN, Guaranteed by design
0.10
1
µA
4
FN9202.2
May 10, 2006