ISL6123 Datasheet, PDF (4/23 Pages) Intersil Corporation – Power Sequencing Controllers

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Pin Descriptions
PIN NUMBER
PIN
NAME
ISL6123, ISL6124, ISL6126,
ISL6125
ISL6130 ISL6127 ISL6128
DESCRIPTION
VDD
23
23
23
23 Chip Bias. Bias IC from nominal 1.5V to 5V.
GND
10
10
10
10 Bias Return. IC ground.
ENABLE_1/
1
ENABLE_1
ENABLE_2/
NC
ENABLE_2
1
1
1
Input to start on/off sequencing. Input to initiate start of programmed
sequencing of supplies on or off. Enable functionality disabled for 10ms after
UVLO is satisfied. ISL6123 and ISL6130 have ENABLE, and ISL6124,
NC
NC
11 _{ISL6125, ISL6126 and ISL6127 have ENABLE. Only ISL6128 has two ENABLE}
inputs; one for each 2-channel grouping. ENABLE_1 is for (A, B), and
ENABLE_2 is for (C, D).
RESET
24
RESET_2
NC
24
24
24 RESET Output. RESET provides low signal 150ms after all GATEs are fully
NC
NC
9
enhanced. Delay is for stabilization of output voltages. RESET asserts low
upon UVLO not being satisfied or ENABLE/ENABLE being deasserted. RESET
outputs are open-drain, N-channel FET and are guaranteed to be in correct
state for VDD down to 1V and are filtered to ignore fast transients on VDD and
UVLO_X.
RESET_2 only exists on ISL6128 for (C, D) group I/O.
UVLO_A
20
UVLO_B
12
UVLO_C
17
20
20
20 Undervoltage Lockout/Monitoring Input. Provides a programmable UV lockout
referenced to an internal 0.633V reference. Filtered to ignore short (<30µs)
12
12
12 _{transients below programmed UVLO level.}
17
17
17
UVLO_D
14
14
14
14
DLY_ON_A
21
DLY_ON_B
8
DLY_ON_C
16
-
-
21 Gate On Delay Timer Output. Allows programming of delay and sequence for
-
-
8
VOUT turn-on using a capacitor to ground. Each capacitor charged with 1µA
10ms after turn-on initiated by ENABLE/ENABLE. Internal current source
-
-
16 _{provides delay to associated FET GATE turn-on.}
DLY_ON_D
15
-
-
15
DLY_OFF_A
18
DLY_OFF_B
13
DLY_OFF_C
3
18
-
18 Gate Off Delay Timer Output. Allows programming of delay and sequence for
13
-
13
VOUT turn-off through ENABLE/ENABLE via a capacitor to ground. Each
capacitor charged with 1µA internal current source to an internal reference
3
-
3
voltage, causing corresponding gate to be pulled down, thus turning off FET.
DLY_OFF_D
4
4
-
4
GATE_A
2
GATE_B
5
GATE_C
6
2
2
2
FET Gate Drive Output. Drives external FETs with 1µA current source to soft-
5
5
5
start ramp into load.
On ISL6125 only, these are open drain outputs that can be pulled up to a
6
6
6
maximum of VDD voltage.
GATE_D
7
7
7
7
SYSRST
22
-
22
-
System Reset I/O. As an input, allows for immediate and unconditional latch-off
of all GATE outputs when driven low. This input can also be used to initiate
programmed sequence with ‘zero’ wait (no 10ms stabilization delay) from input
signal on this pin being driven high to first GATE. As an output, when there is a UV
condition, this pin pulls low. If common to other SYSRST pins in a multiple IC
configuration, it causes immediate and unconditional latch-off of all other GATEs
on all other ISL612X sequencers.
GND
EPAD
EPAD
EPAD
EPAD Ground. Die Substrate
NC
9, 19
8, 9, 11, 3, 4, 8, 9, 19, 22 No Connect
15, 16, 11, 13,
19, 21, 22 15,16,18,
19, 21
4
FN9005.11
August 25, 2011