ISL6123 Datasheet, PDF (11/23 Pages) Intersil Corporation – Power Sequencing Controllers

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Typical Performance Curves (Continued)
GATE
5VOUT
3.3VOUT
SYSRST
2V/DIV
1µs/DIV
FIGURE 8. SYSRST LOW TO OUTPUT LATCH-OFF
Using the ISL6123EVAL1Z
Platform
The ISL6123EVAL1Z platform layout illustrates the small
implementation size for a typical 4-rail sequencing application.
The platform allows evaluation of the ISL6123, ISL6124,
ISL6126, ISL6127, ISL6128 and ISL6130. See Figure 17 for
schematic and photograph of evaluation platform and Table 2
for the component listing.
Significant current loading of the GATE or capacitive loading of
the DLY_ON and OFF pins will affect functionality and
performance.
The default configuration of the ISL6123EVAL1Z circuit is built
around the following design assumptions:
1. Using the ISL6123IR.
2. The four supplies being sequenced are 5V (IN_A), 3.3V
(IN_B), 2.5V (IN_D) and 1.5V (IN_C). The UVLO levels are
~80% of nominal voltages. Resistors are chosen such that
the total resistance of each divider is ~ 10k. Using standard
value resistors to approximate 80% of nominal voltage
supply = 0.63V on UVLO input.
3. The desired order turn-on sequence is 5V first, then 3.3V
about 12ms later, then the 2.5V supply about 19ms later,
and lastly, the 1.5V supply about 40ms later.
4. The desired turn-off sequence is first both 1.5V and 3.3V
supplies at the same time, then the 2.5V supply about
50ms later, and lastly, the 5V supply about 72ms after that.
LED off indicates sequence has completed and RESET has
released and pulled high.
The board is shipped with the ISL6123 installed and with each
of the other released variant types loose packed. As this
sequencer family has a common function pinout for most
variants, no major modifications to the board are necessary to
evaluate the other ICs. See Figure 18 for the ISL6125-specific
evaluation board and schematic.
11
All scope shots are taken from the ISL6123EVAL1Z board.
Figures 9 and 10 illustrate the desired turn-on and turn-off
sequences, respectively. The sequencing order and delay
between voltages sequencing is set by external capacitance
values; sequences other than those illustrated can be
accomplished.
Figures 11 and 12 illustrate the timing relationships between the
EN input; the RESET, DLY and GATE outputs; and the VOUT voltage
for a single channel being turned on and off, respectively. RESET
is not shown in Figure 11 as it asserts 160ms after the last GATE
goes high.
All IC family variants share a similar function for DLY_X capacitor
charging and GATE and RESET operation. Figures 13 through 16
illustrate the principal feature and functional differences for each
of the ISL6125, ISL6126, ISL6127 and ISL6128 variants.
Figure 13 shows the ISL6125 open-drain outputs being
sequenced on and off, along with the RESET relationship, which is
similar to all other family variants.
Figure 14 illustrates the independent input feature of the
ISL6126 which, once EN is low, allows for each UVLO to be
individually satisfied and for its associated GATE to turn on. Only
when the last variable VIN is satisfied, as shown, does RESET
release, to signal all input voltages are valid.
Figure 15 shows the ISL6127 pre-programmed ABCD turn-on
and DCBA turn-off order of sequencing, with minimal
non-adjustable delay between each.
Figure 16 demonstrates the independence of the ISL6128, the
redundant 2-rail sequencer. It shows that either one of the two
groups can be turned off, and the ABCD order of restart with
capacitor programmable delay, once both EN inputs are pulled
low.
FN9005.11
August 25, 2011