ISL5927 Datasheet, PDF (4/13 Pages) Intersil Corporation – Dual 14-Bit, +3.3V, 260+MSPS, High Speed D/A Converter

ISL5927
Pin Descriptions
PIN NO.
PIN NAME
PIN DESCRIPTION
11, 19, 26
AGND
Analog ground.
13, 24
28
A_VDD
CLK
Analog supply (+2.7V to +3.6V).
Clock Input.
27
DGND
Connect to digital ground.
10
20
14, 23
D_VDD
FSADJ
NC
Digital supply (+2.7V to +3.6V).
Full scale current adjust. Use a resistor to ground to adjust full scale output current. Full scale output
current = 32 x V_FSADJ/R_SET.
Not internally connected. Recommend no connect.
12, 25
ICOMP, QCOMP Compensation pin for internal bias generation. Each pin should be individually decoupled to AGND with
a 0.1µF capacitor.
1-8, 29-48 ID13-ID0, QD13-QD0 Digital data input ports. Bit 13 is most significant bit (MSB) and bit 0 is the least significant bit (LSB).
15, 22
IOUTA, QOUTA Current outputs of the device. Full scale output current is achieved when all input bits are set to binary 1.
16, 21
IOUTB, QOUTB Complementary current outputs of the device. Full scale output current is achieved on the complementary
outputs when all input bits are set to binary 0.
17
REFIO
Reference voltage input if Internal reference is disabled. The internal reference is not intended to drive an
external load. Use 0.1µF cap to ground when internal reference is enabled.
18
REFLO
Connect to analog ground to enable internal 1.2V reference or connect to AV_DD to disable internal reference.
9
SLEEP
Connect to digital ground or leave floating for normal operation. Connect to DV_DD for sleep mode.
4