ISL5927 Datasheet, PDF (12/13 Pages) Intersil Corporation – Dual 14-Bit, +3.3V, 260+MSPS, High Speed D/A Converter

ISL5927
theoretically improving the even order harmonic rejection,
but likely reducing the signal swing available due to the
output voltage compliance range limitations.
R_EQ = 0.5 x (R_LOAD//R_DIFF)
AT EACH OUTPUT
ISL5927
OUTA
R_DIFF
OUTB
V_OUT = (2 x OUTA x R_EQ)V
1:1
R_LOAD
R_LOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 13. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
Timing Diagram
R_EQ = 0.5 x (R_LOAD // R_DIFF// R_A), WHERE R_A=R_B
AT EACH OUTPUT
ISL5927
OUTA
OUTB
R_A
R_DIFF
R_B
V_OUT = (2 x OUTA x R_EQ)V
R_LOAD
R_LOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 14. ALTERNATIVE OUTPUT LOADING
Propagation Delay
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous
data. The propagation delay is therefore 1/CLK, plus <2ns of
processing. See Figure 15.
Test Service
Intersil offers customer-specific testing of converters with a
service called Testdrive. To submit a request, fill out the
Testdrive form at www.intersil.com/testdrive. Or, send a
request to the technical support center.
CLK
D13-D0
t_PW1
t_PW2
t_SU
W₀
t_HLD
t_SU
W₁
t_HLD
t_SU
W₂
t_HLD
50%
W₃
I_OUT
t_PD
OUTPUT=W_-1
t_PD
OUTPUT=W₀
OUTPUT=W₁
FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
12