ISL45042_07 Datasheet, PDF (4/8 Pages) Intersil Corporation – LCD Module Calibrator

ISL45042
Electrical Specifications
PARAMETER
Test Conditions: V_DD = 3V, AV_DD = 10V, OUT = 5V, R_SET = 24.9kΩ; Unless Otherwise Specified.
Typicals are at T_A = +25°C (Continued)
SYMBOL
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 8)
MAX
TYP (Note 8) UNITS
CTL EEPROM Programming
Signal Time
CTL_PT
>4.9V
Full
200
-
-
µs
Programming Time
SET Voltage Resolution
SET Differential Nonlinearity
SET Zero-Scale Error
SET Full-Scale Error
SET Current
SET External Resistance
AVDD to SET Voltage Attenuation
P_T
SET_VR
SET_DN
SET_ZSE
SET_FSE
ISET
SET_ER
AVDD to SET
(Note 4)
Monotonic Over-Temperature
Through R_SET (Note 7)
To GND, AV_DD = 20V
To GND, AV_DD = 4.5V
Full
100
ms
Full
7
7
7
Bits
Full
-
-
±1
LSB
Full
-
-
±2
LSB
Full
-
-
±8
LSB
Full
-
20
-
µA
Full
10
-
200
kΩ
Full
2.25
-
45
kΩ
Full
-
1:20
-
V/V
OUT Settling Time
OUT_ST
To ±0.5 LSB Error Band (Note 5)
Full
-
20
-
µs
OUT Voltage Range
V_OUT
Full VSET + 0.5V
-
13
V
OUT Voltage Drift
OUT_VD
(Note 5)
25 to 55
-
<10
-
mV
NOTES:
2. CTL signal only needs to be greater than 4.9V to program EEPROM.
3. Tested at AV_DD = 20V.
4. The Counter value is set to mid-scale ±4 LSB’s in the Production.
5. Simulated and Determined via Design and NOT Directly Tested.
6. Simulated Maximum Current Draw when Programming EEPROM is 23mA; should be considered when designing Power Supply.
7. A Typical Current of 20µA is Calculated using the AV_DD = 10V and R_SET = 24.9kΩ. Reference “RSET Resistor” on page 6.
8. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
AVDD
ISL45042
CTL
CE
SET
OUT
R_SET
AVDD
I_SINK
R₁
R₂
+
-
VCOM
COLUMN
DRIVER
Application Information
The application circuit to adjust the V_COM voltage in an LCD
panel is shown in Figure 1. The ISL45042 has a 128-step
sink current resolution. The output is connected to an
external voltage divider that results in decreasing the output
V_COM voltage as you increase the ISL45042 sink current.
CTL Pin
The adjustment of the output V_COM voltage and the
programming of the non-volatile memory are provided
through a single pin called CTL when the CE pin is high.
The output VCOM voltage is increased with a mid (V_DD/2) to
high transition (0.8*V_DD) on the CTL pin. The output V_COM
voltage is decreased with a mid (V_DD/2) to low transition
(0.3*V_DD) on the CTL pin (Reference Figure 7). Once the
minimum or maximum value is reached on the 128 steps,
the device will not overflow or underflow beyond that
minimum or maximum value.
SINGLE PIXEL
IN LCD PANEL
FIGURE 1. V_COM ADJUSTMENT IN AN LCD PANEL
Programming of the non-volatile memory occurs when the
CTL pin exceeds 4.9V. The CTL signal needs to remain
above 4.9V for more than 200µs. The level and timing
needed to program the non-volatile memory is given in
4
FN6072.7
August 29, 2007