ISL45042_07 Datasheet, PDF (2/8 Pages) Intersil Corporation – LCD Module Calibrator

ISL45042
Pin Descriptions
PIN
FUNCTION
OUT
Adjustable Sink Current Output Pin. The current sinks into the OUT pin is equal to the DAC setting times the maximum adjustable sink
current divided by 128. See SET pin function description for the maximum adjustable sink current setting.
AVDD High-Voltage Analog Supply. Connects to top of external resistor divider to determine the VCOM voltage. Typically 10V to 20V. Bypass
to GND with 0.1µF de-coupling capacitor.
N/C No Connect. Not internally connected.
GND Ground connection.
VDD ISL45042 power supply input. Bypass to GND with 0.1µF de-coupling capacitor.
CTL Internal Counter Up/Down Control and Internal EEPROM Programming Control Input. If CE is high, a mid-to-low transition increments
the 7-Bit counter, raising the DAC setting, increasing the OUT sink current, and lowering the divider voltage at OUT. A mid-to-high
transition decrements the 7-Bit counter, lowering the DAC setting, decreasing the OUT sink current, and increasing the divider voltage
at OUT. Applying 4.9V and above with appropriately arranged timing will overwrite EEPROM with the contents in the 7-Bit counter.
See EEPROM Programming section for details.
CE
Counter Enable Pin. Connect CE to VDD to enable adjustment of the output sink current. Float or connect CE to GND to prevent
further adjustment or programming (Note: the CE pin has an internal pull-down resistor).
SET Maximum Sink Current Adjustment Point. Connect a resistor from the SET pin to GND to set the maximum adjustable sink current of
the OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided by RSET.
Block Diagram
CE
400kΩ
TO
500kΩ
CTL
DIGITAL INTERFACE
WITH THRESHOLD
SENSORS
UP
DWN
PWRUP
POR
PRGM
ISL45042
IBIAS
UP/DOWN COUNTER
WITH PRESET
LATCHES
AVDD
ANALOG DCP AND
CURRENT OUTPUT
BLOCK
IOUT
SET
POR
PRGM
READ
PRGM MEMORY
EEPROM
OR
NVL MEMORY
GND
VDD
2
FN6072.7
August 29, 2007