ISL29029_14 Datasheet, PDF (4/16 Pages) Intersil Corporation – Low Power Ambient Light and Proximity Sensor with Intelligent Interrupt and Sleep Modes

ISL29029
Electrical Specifications V_DD = 3.0V, T_A = +25°C, R_EXT = 499kΩ 1% tolerance. (Continued)
PARAMETER
DESCRIPTION
CONDITION
MIN TYP MAX UNIT
I_{IRDR_0} IRDR Sink Current
PROX_DR = 0; V_IRDR = 0.5V
90 110 130 mA
I_{IRDR_1} IRDR Sink Current
PROX_DR = 1; V_IRDR = 0.5V
220
mA
I_{IRDR_LEAK} IRDR Leakage Current
PROX_EN = 0; V_DD = 3.63V (Note 10)
0.001 1 µA
V_IRDR
Acceptable Voltage Range on IRDR Pin
Register bit PROX_DR = 0
0.5
4.3 V
t_PULSE Net I_IRDR On Time Per PROX Reading
100
µs
V_REF
F_I2C
V_I2C
Voltage of R_EXT Pin
I²C Clock Rate Range
Supply Voltage Range for I²C Interface
0.51
V
400 kHz
1.7
3.63 V
V_IL
SCL and SDA Input Low Voltage
0.55 V
V_IH
SCL and SDA Input High Voltage
1.25
V
I_SDA
SDA Current Sinking Capability
V_OL = 0.4V
35
mA
I_INT
INT Current Sinking Capability
V_OL = 0.4V
35
mA
PSRR_IRDR (ΔI_IRDR)/(ΔV_IRDR)
PROX_DR = 0; V_IRDR = 0.5V to 4.3V
4
mA/V
NOTES:
7. Nonlinearity is defined as: [(Measured Counts at 53 lux)-(Expected Counts at 53 lux)]/4095. Expected counts are calculated using an endpoint linear-
fit trendline from measurements at 0 lux and 90 lux.
8. An LED is used in production test. The LED irradiance is calibrated to produce the same DATA count against a fluorescent light source of the same lux
level.
9. An 850nm infrared LED is used to test PROX/IR sensitivity in an internal test mode.
10. Ability to guarantee I_IRDR leakage of ~1nA is limited by test hardware.
11. For ALS applications under light-distorting glass, please see the section titled ALS Range 1 Considerations.
I2C Electrical Specifications For SCL and SDA unless otherwise noted, V_DD = 3V, T_A = +25°C, R_EXT = 499kΩ 1% tolerance
(Note 12).
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP MAX UNIT
V_I2C
Supply Voltage Range for I²C Interface
f_SCL
SCL Clock Frequency
V_IL
SCL and SDA Input Low Voltage
V_IH
SCL and SDA Input High Voltage
V_hys
Hysteresis of Schmitt Trigger Input
V_OL
Low-level output voltage (open-drain) at 4mA sink
current
1.7
1.25
0.05V_DD
3.63 V
400 kHz
0.55 V
V
V
0.4 V
I_i
Input Leakage for each SDA, SCL pin
t_SP
Pulse width of spikes that must be suppressed by
the input filter
-10
10 µA
50 ns
t_AA
SCL Falling Edge to SDA Output Data Valid
C_i
Capacitance for each SDA and SCL pin
t_HD:STA Hold Time (Repeated) START Condition
After this period, the first clock pulse is
600
generated
900 ns
10 pF
ns
t_LOW
LOW Period of the SCL clock
Measured at the 30% of VDD crossing
1300
ns
t_HIGH
HIGH period of the SCL Clock
600
ns
t_SU:STA
Set-up Time for a Repeated START Condition
600
ns
t_HD:DAT Data Hold Time
30
ns
4
FN7682.0
November 23, 2010