ISL1219 Datasheet, PDF (4/24 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM and Event Detection

ISL1219
I²C Interface Specifications Test Conditions: V_DD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 9)
MAX
TYP (Note 4) (Note 9) UNITS NOTES
V_IL
SDA and SCL Input Buffer LOW
Voltage
-0.3
0.3 x V_DD V
V_IH
SDA and SCL Input Buffer HIGH
Voltage
0.7 x V_DD
V_DD + 0.3 V
Hysteresis SDA and SCL Input Buffer Hysteresis
V_OL
SDA Output Buffer LOW Voltage,
V_DD = 5V, I_OL = 3mA
Sinking 3mA
0.05 x V_DD
V
0.4
V
Cpin
f_SCL
t_IN
SDA and SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
T_A = +25°C, f = 1MHz,
V_DD = 5V, V_IN = 0V, V_OUT = 0V
Any pulse narrower than the
max spec is suppressed.
10
pF
400
kHz
50
ns
t_AA
t_BUF
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30%
Valid
of V_DD, until SDA exits the 30%
to 70% of V_DD window.
Time the Bus Must be Free before the
Start of a New Transmission
SDA crossing 70% of V_DD
during a STOP condition, to
SDA crossing 70% of V_DD
during the following START
condition.
1300
900
ns
ns
t_LOW
Clock LOW Time
Measured at the 30% of V_DD
1300
ns
crossing.
t_HIGH
Clock HIGH Time
Measured at the 70% of V_DD
600
ns
crossing.
t_SU:STA START Condition Setup Time
t_HD:STA START Condition Hold Time
t_SU:DAT Input Data Setup Time
t_HD:DAT Input Data Hold Time
t_SU:STO STOP Condition Setup Time
t_HD:STO STOP Condition Hold Time
t_DH
Output Data Hold Time
t_R
SDA and SCL Rise Time
t_F
SDA and SCL Fall Time
SCL rising edge to SDA falling
600
edge. Both crossing 70% of V_DD.
From SDA falling edge crossing
600
30% of V_DD to SCL falling edge
crossing 70% of V_DD.
From SDA exiting the 30% to
100
70% of V_DD window, to SCL
rising edge crossing 30% of V_DD.
From SCL falling edge crossing
0
30% of V_DD to SDA entering the
30% to 70% of V_DD window.
From SCL rising edge crossing
600
70% of V_DD, to SDA rising edge
crossing 30% of V_DD.
From SDA rising edge to SCL
600
falling edge. Both crossing 70%
of V_DD.
From SCL falling edge crossing
0
30% of V_DD, until SDA enters
the 30% to 70% of V_DD window.
From 30% to 70% of V_DD.
20 + 0.1 x Cb
From 70% to 30% of V_DD.
20 +
0.1 x Cb
ns
ns
ns
900
ns
ns
ns
ns
300
ns
7
300
ns
7
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
7
4
FN6314.2
July 15, 2010