ICL7667CBAZA-T Datasheet, PDF (4/10 Pages) Intersil Corporation – Dual Power MOSFET Driver

Typical Performance Curves (Continued)
ICL7667
100
V+ = 15V
10
V+ = 5V
1
100µA
10k
C_L = 1nF
100k
1M
FREQUENCY (Hz)
10M
FIGURE 5. I_V+ vs FREQUENCY
50
40
30
20
10
0
5
t_f
t_D1
C_L = 1nF
10
15
V+ (V)
FIGURE 7. DELAY AND FALL TIMES vs V+
Detailed Description
The ICL7667 is a dual high-power CMOS inverter whose
inputs respond to TTL levels while the outputs can swing as
high as 15V. Its high output current enables it to rapidly
charge and discharge the gate capacitance of power
MOSFETs, minimizing the switching losses in switchmode
power supplies. Since the output stage is CMOS, the output
will swing to within millivolts of both V- and V+ without any
external parts or extra power supplies as required by the
DS0026/56 family. Although most specifications are at
V+ = 15V, the propagation delays and specifications are
almost independent of V+.
In addition to power MOS drivers, the ICL7667 is well suited
for other applications such as bus, control signal, and clock
drivers on large memory of microprocessor boards, where
the load capacitance is large and low propagation delays are
required. Other potential applications include peripheral
power drivers and charge-pump voltage inverters.
4
100
10
V+ = 15V
1
V+ = 5V
100mA
10k
C_L = 10pF
100k
1M
10M
FREQUENCY (Hz)
FIGURE 6. NO LOAD I_V+ vs FREQUENCY
50
40
30
t_r = T_D2
20
10
C_L = 10pF
0
5
10
15
V+ (V)
FIGURE 8. RISE TIME vs V+
Input Stage
The input stage is a large N-Channel FET with a P-Channel
constant-current source. This circuit has a threshold of about
1.5V, relatively independent of the V+ voltage. This means
that the inputs will be directly compatible with TTL over the
entire 4.5V - 15V V+ range. Being CMOS, the inputs draw
less than 1µA of current over the entire input voltage range
of V- to V+. The quiescent current or no load supply current
of the ICL7667 is affected by the input voltage, going to
nearly zero when the inputs are at the 0 logic level and rising
to 7mA maximum when both inputs are at the 1 logic level. A
small amount of hysteresis, about 50mV to 100mV at the
input, is generated by positive feedback around the second
stage.
Output Stage
The ICL7667 output is a high-power CMOS inverter,
swinging between V- and V+. At V+ = 15V, the output
impedance of the inverter is typically 7Ω. The high peak
FN2853.6
April 29, 2010