HC-5560_03 Datasheet, PDF (4/10 Pages) Intersil Corporation – PCM Transcoder

HC-5560
Pin Descriptions (Continued)
PIN NUMBER FUNCTION
DESCRIPTION
14
16, 17
LTE
OUT1, OUT2
Loop Test Enable, this pin selects between normal and loop back operation. A logic ‘0’ selects normal
operation where encode and decode are independent and asynchronous. A logic ‘1’ selects a loop back
condition where OUT1 is internally connected to A_IN and OUT2 is internally connected to B_IN. A decode clock
must be supplied.
Outputs representing the ternary encoded NRZ Data In signal for line transmission. OUT1 and OUT2 are in
return to zero form and are clocked out on the positive going edge of CLK ENC. The length of OUT1 and
OUT2 is set by the length of the positive clock pulse.
18
Reset
A logic ‘0’ on this pin resets all internal registers to zero. A logic ‘1’ allows normal operation of all internal
registers.
19
Output Enable A logic ‘1’ on this pin forces outputs OUT1 and OUT2 to zero. A logic ‘0’ allows normal operation.
20
V_DD
Power to chip.
Functional Description
The HC-5560 TRANSCODER can be divided into six sections:
transmission (coding), reception (decoding), error detection, all
ones detection, testing functions, and output controls.
The transmitter codes a non-return to zero (NRZ) binary
unipolar input signal (NRZ Data In) into two binary unipolar
return to zero (RZ) output signals (OUT1, OUT2). These
output signals represent the NRZ data stream modified
according to the selected encoding scheme (i.e., AMl, B8ZS,
B6ZS, HDB3) and are externally mixed together (usually via
a transistor or transformer network) to create a ternary
bipolar signal for driving transmission lines.
The receiver accepts as its input the ternary data from the
transmission line that has been externally split into two binary
unipolar return to zero signals (A_IN and B_IN). These signals are
decoded, according to the rules of the selected line code into
one binary unipolar NRZ output signal (NRz Data Out).
The encoder and decoder sections of the chip perform
independently (excluding loopback condition) and may
operate simultaneously.
The Error output signal is active high for one cycle of CLK
DEC upon the detection of any bipolar violation in the
received A_IN and B_IN signals that is not part of the selected
line coding scheme. The bipolar violation is not removed,
however, and shows up as a pulse in the NRZ Data Out
signal. In addition, the Error output signal monitors the
received A_IN and B_IN signals for a string of zeros that
violates the maximum consecutive zeros allowed for the
selected line coding scheme (i.e., 15 for AMI, 8 for B8ZS, 6
for B6ZS, and 4 for HDB3). ln the event that an excessive
amount of zeros is detected, the Error output signal will be
active high for one cycle of CLK DEC during the zero that
exceeds the maximum number. In the case that a high level
should simultaneously appear on both received input signals
A_IN and B_IN a logical one is assumed and appears on the
NRZ Data Out stream with the Error output active.
An input signal received at inputs A_IN and B_IN that consists
of all ones (or marks) is detected and signaled by a high
level at the Alarm Indication Signal (AlS) output. This is also
known as Blue Code. The AlS output is set to a high level
when less than three zeros are received during one period of
Reset AIS immediately followed by another period of Reset
AlS containing less than three zeros. The AIS output is reset
to a low level upon the first period of Reset AlS containing 3
or more zeros.
A logic high level on LTE enables a loopback condition
where OUT1 is internally connected to A_IN and OUT2 is
internally connected to B_IN (this disables inputs A_IN and B_IN
to external signals). In this condition, NRZ Data In appears
at NRZ Data Out (delayed by the amount of clock cycles it
takes to encode and decode the selected line code). A
decode clock must be supplied for this operation.
The output controls are Output Enable and Force AlS. These
pins allow normal operation, force OUT1 and OUT2 to zero,
or force OUT1 and OUT2 to output all ones (AIS condition).
Line Code Descriptions
AMl, Alternate Mark Inversion, is used primarily in North
American T1 (1.544MHz) and T1C (3.152MHz) carriers.
Zeros are coded as the absence of a pulse and ones are
coded alternately as positive or negative pulses. This type of
coding reduces the average voltage level to zero to eliminate
DC spectral components, thereby eliminating DC wander. To
simplify timing recovery, logic 1’s are encoded with 50% duty
cycle pulses.
e.g.,
PCM CODE
0 0 0 1 01 1 1 0 1 0 0 00 01
AMI CODE
To facilitate timing maintenance at regenerative repeaters
along a transmission path, a minimum pulse density of logic
1’s is required. Using AMl, there is a possibility of long
strings of zeros and the required density may not always
exist, leading to timing jitter and therefore higher error rates.
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