HC-5560_03 Datasheet, PDF (3/10 Pages) Intersil Corporation – PCM Transcoder

HC-5560
Electrical Specifications Unless Otherwise Specified, Typical parameters at 25^oC, Min-Max parameters are over operating
temperature range. V_DD = 5V. (Continued)
PARAMETER
SYMBOL
FIGURE
MIN
TYP
MAX
UNITS
NRZ-Data In to CLK ENC Data Setup Time
Data Hold Time
A_IN, B_IN to CLK DEC Data Setup Time
Data Hold Time
CLK ENC to OUT1, OUT2
OUT1, OUT2 Pulse Width (CLK ENC Duty Cycle = 50%)
f_CL = 1.544MHz
f_CL = 2.048MHz
f_CL = 6.3212MHz
f_CL = 8.448MHz
CLK DEC to NRZ-Data Out
Setup Time CLK DEC to Reset AlS
Hold Time of Reset AlS = ‘0’
Setup Time Reset AlS = ‘1’ to CLK DEC
Reset AlS to AIS Output
CLK DEC to Error Output
t_S
1
20
-
-
ns
t_H
1
20
-
-
ns
t_S
2
15
-
-
ns
t_H
2
5
-
-
ns
t_DD
1
-
23
80
ns
t_W
1
-
324
-
ns
t_W
1
-
224
-
ns
t_W
1
-
79
-
ns
t_W
1
-
58
-
ns
t_DD
2
-
25
54
ns
t_S2
3
35
-
-
ns
t_H2
3
20
-
-
ns
t_S2
3
0
-
-
ns
t_PD5
3
-
-
42
ns
t_PD4
3
-
-
62
ns
Pin Descriptions
PIN NUMBER
1
2, 5
3
4
6
7
8, 9
10
11
12
13, 15
FUNCTION
Force AIS
Mode Select 1,
Mode Select 2
NRZ Data In
CLK ENC
NRZ Data Out
CLK DEC
Reset AIS, AlS
V_SS
Error
Clock
A_IN, B_IN
DESCRIPTION
Pin 19 must be at logic ‘0’ to enable this pin. A logic ‘1’ on this pin forces OUT1 and OUT2 to all ‘1’s. A logic
‘0’ on this pin allows normal operation.
MS1
0
0
1
1
MS2
0
1
0
1
Functions As
AMI
B8ZS
B6ZS
HDB3
Input data to be encoded into ternary form. The data is clocked by the negative going edge of CLK ENC.
Clock encoder, clock for encoding data at NRZ Data In.
Decoded data from ternary inputs A_IN and B_IN.
Clock decoder, clock for decoding ternary data on inputs A_IN and B_IN.
Logic ‘0’ on Reset AIS resets a decoded zero counter and either resets AIS output to zero provided 3 or more
zeros have been decoded in the preceding Reset AIS period or sets AlS to ‘1’ if less than 3 zeros have been
decoded in the preceding two Reset AlS periods. A period of Reset AlS is defined from the bit following the
bit during which Reset AlS makes a high to low transition to the bit during which Reset AIS makes the next
high to low transition.
Ground reference.
A logic ‘1’ indicates that a violation of the line coding scheme has been decoded.
“OR” function of A_IN and B_IN for clock regeneration when pin 14 is at logic ‘0’, “OR” function of OUT1 and
OUT2 when pin 14 is at logic ‘1’.
Inputs representing the received PCM signal. A_IN = ‘1’ represents a positive going ‘1’ and B_IN = ‘1’ represents
a negative going ‘1’. A_IN and B_IN are sampled by the positive going edge of CLK DEC. A_IN and B_IN may be
interchanged.
3