HC-55564883 Datasheet, PDF (4/5 Pages) Intersil Corporation – Continuously Variable Slope Delta-Modulator (CVSD)

HC-55564/883
TABLE 3. ELECTRICL PERFORMANCE CHARACTERISTICS (Continued)
Devices Characterized at: V_DD = +5.0V, T_A = +25^oC, Operating Temperature, fclk = 16kHz Clock Sampling Rate.
ENC/DDC = ENC = Encode Mode, Unless Otherwise Specified. (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTE
TEMPERATURE
TYP MAX UNITS
Audio Input Voltage
Audio Output Voltage
Input Impedance
A_IN
A_IN = 100Hz
A_OUT
A_IN = 100Hz
Z_IN
A_IN = 100Hz
4, 12
5, 12
6, 12
+25^oC
+125^oC, -55^oC
+25^oC
+125^oC, -55^oC
+25^oC
+125^oC, -55^oC
-
1.2
V_RMS
-
1.2
V_RMS
-
1.2
V_RMS
-
1.2
V_RMS
150
500
kΩ
150
500
kΩ
Output Impedance
Z_OUT
A_IN = 100Hz
6, 12
+25^oC
35
25
kΩ
+125^oC, -55^oC
35
25
kΩ
Transfer Gain
A_E-D
A_IN = 0.775 V_RMS at 11, 12
+25^oC
-2
+2
dB
100Hz
-55^oC, +125^oC
-2
+2
dB
Resolution
RES
A_IN at 100Hz. Note 8
12, 13
+25^oC
0.3
-
% of
Supply
MIN Step Size
MSS
7, 12
+25^oC
0.10
0.14
% of
Supply
Clamping Threshold
V_CTH
10, 12
+25^oC
0.70
0.90
F.S.
NOTES:
1. There is one NRZ (Non-Return Zero) data bit per clock period. Data is clocked out on the negative clock edge. Data is clocked into the CVSD
on the positive going edge (see Figure 2). Clock may be run at less than 9kbps.
2. Logic inputs are CMOS compatible at supply voltage and are diode protected. Digital data input is NRZ at clock rate.
3. Logic outputs are CMOS compatible at supply voltage and will withstand short-circuits to V_DD or ground; however, the short circuit duty cycle
must not exceed 5% in order to maintain an acceptable current density level. Digital data output is NRZ and changes with negative clock tran-
sitions. Each output will drive one LS TTL loads.
4. Recommended voice input range for best voice performance. Should be externally AC coupled.
5. May be used for side-tone in encode mode. Should be externally AC coupled.
6. Presents series impedance with audio signal. Zero signal reference is approximately V_DD/2. Varies with audio input level by ±2dB.
7. The minimum audio output voltage change that can be produced by the internal DAC.
8. The “quieting” pattern or idle-channel audio output steps at 1/2 the bit rate, changing state on negative clock transitions.
9. A logic “0” will appear at the AGC output pin when the recovered signal reaches one-half of full-scale value (positive or negative), i.e. at V_DD/2
±25% of V_DD.
10. The recovered signal will be clamped, and the computation will be inhibited, when the recovered signal reaches three-quarters of full-scale val-
ue, and will unclamp when it falls below this value (positive or negative).
11. No load condition measured from audio in to audio out.
12. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are charac-
terized upon initial design release and upon design changes which would affect these characteristics.
13. The minimum audio input voltage above which encoding is guaranteed to take place.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
SUBGROUPS (SEE TABLE 1)
Interim Electrical Parameters (Pre Burn-In)
Final Electrical Test Parameters
Group A Test Requirements
1
1 (Note 1), 2, 3
1, 2, 3
Groups C and D Endpoints
1
NOTE:
1. PDA applies to Subgroup 1 only.
4