HC-55564883 Datasheet, PDF (2/5 Pages) Intersil Corporation – Continuously Variable Slope Delta-Modulator (CVSD)

HC-55564/883
Pin Description
PIN NO.
14 LEAD
DIP
PIN NO.
20 LEAD
LCC
SYMBOL
DESCRIPTION
1
2
V_DD
Positive Supply Voltage. Voltage range is +3.2V to +6.0V.
2
3
Analog Analog Ground connection to D/A ladders and comparator.
GND
3
4
A_OUT Audio Out recovered from 10-bit DAC. May be used as side tone at the transmitter. Presents
approximately 75kΩ source with DC offset of V_DD/2. Within ±2dB of Audio Input. Should be externally
AC coupled.
4
6
AGC Automatic Gain Control output. A logic low level will appear at this output when the recovered signal ex-
cursion reaches one-half of full scale value. In each half cycle full scale is V_DD/2. The mark-space ratio
is proportional to the average signal level.
5
8
A_IN
Audio Input to comparator. Should be externally AC coupled. Presents approximately 200kΩ in series
with V_DD/2.
6, 7
1, 5, 7, 9,
NC
No internal connection is made to these pins.
10, 11, 15,
17
8
12
Digital Logic ground. 0V reference for all logic inputs and outputs.
GND
9
13
Clock Sampling rate clock. In the decode mode, must be synchronized with the digital input data such that the
data is valid at the positive clock transition. In the encode mode, the digital data is clocked out on the
negative going clock transition. The clock rate equals the data rate.
10
14
Encode/ A single CVSD can provide half-duplex operation. The encode or decode function is selected by the logic
Decode level applied to this input. A low level selects the encode mode, a high level the decode mode.
11
16
APT Alternate Plain Text input. Activating this input caused a digital quieting pattern to be transmitted, however;
internally the CVSD is still functional and a signal is still available at the A_OUT port. Active low.
12
18
Digital In Input for the received digital NRZ data.
13
19
FZ
Force Zero input. Activating this input resets the internal logic and forces the digital output and the recov-
ered audio output into the “quieting” condition. An alternating 1-0 pattern appears at the digital output at
1/2 the clock rate. When this is decoded by a receive CVSD, a 10mV_P-P inaudible signal appears at audio
output. Active low.
14
20
Digital Out Output for transmitted digital NRZ data.
NOTE:
1. No active input should be left in a “floating condition”.
Functional Diagram
(1)
V_DD
(12)
DIGITAL
IN
3V TO 6V _VDD
2
(5)
A_IN
Z_IN
(2)
ANALOG
GND
(3) A_OUT
(SIDE TONE)
Z_OUT
(4) AGC OUT
(10)
ENC/DEC
(11) (13) FORCE
APT
ZERO
(9)
CLOCK
(8) _DIGITAL
GND
RESET
T _{F/F Q}
(14)
DIGITAL
OUT
COMPARATOR
D
3-BIT
SHIFT
REGISTER
10-BIT
DAC
10
RESET
STEP
SIZE
LOGIC
10
10-BIT
DAC
SIGNAL
ESTIMATE
FILTER 1ms
6 _DIGITAL
MODULATOR
±1
SYLLABIC
FILTER
4ms
RESET
2