CD54AC02F3A Datasheet, PDF (4/4 Pages) Intersil Corporation – Quad 2-Input NOR Gate

CD54AC02F3A, CD54ACT02F3A
Switching Specifications Input t_r, t_f = 3ns, C_L = 50pF (Worst Case)
-55^oC TO 125^oC
PARAMETER
AC TYPES
SYMBOL
V_CC (V)
MIN
TYP
MAX
UNITS
Propagation Delay, Input to Output
t_PLH, t_PHL
1.5
-
-
144
ns
3.3 (Note 9)
3
-
20.1
ns
5 (Note 10)
2
-
11.5 (Note 8)
ns
Input Capacitance
Power Dissipation Capacitance
ACT TYPES
C_I
-
C_PD (Note 11)
-
-
-
10
pF
-
55
-
pF
Propagation Delay, Input to Output
t_PLH
t_PHL
5 (Note 10)
2.1
-
12.2 (Note 8)
ns
Input Capacitance
C_I
-
-
-
10
pF
Power Dissipation Capacitance
C_PD (Note 11)
-
-
55
-
pF
NOTES:
8. Limits tested at 100%.
9. 3.3V Min at 3.6V, Max at 3V.
10. 5V Min at 5.5V, Max at 4.5V
11.
CAC_{PD: PisD}u=seVd_Ct_Co₂dfe_i t(eCr_Pm_Din+e
the
C_L)
dynamic
power
consumption
per gate.
ACT: P_D = V_CC2 f_i (C_PD + C_L) + V_CC ∆I_CC where f_i = input frequency, C_L = output load capacitance, V_CC = supply voltage.
Burn-In Test Circuit Connections (Use DC II for F3A Burn-In and AC for Life Test)
DC
CD54AC/ACT02
OPEN
1, 4, 10, 13
DC BURN-IN I
GROUND
2, 3, 5-9, 11,12
V_CC (6V)
14
AC
CD54AC/ACT02
OPEN
-
GROUND
7
1/2 V_CC (3V)
1, 4, 10, 13
NOTE: Each pin except V_CC and Gnd will have a resistor of 2kΩ-47kΩ.
OPEN
1, 4, 10, 13
V_CC (6V)
14
DC BURN-IN II
GROUND
7
V_CC (6V)
2, 3, 5, 6, 8, 9, 11,
12, 14
OSCILLATOR
50kHz
25kHz
2, 3, 5, 6, 8, 9, 11,
-
12
t_r = 3ns
INPUT
LEVEL
V_I
V_O
t_f = 3ns
90%
V_S
10% _GND
V_S
t_PHL
t_PLH
FIGURE 1. PROPAGATION DELAY TIMES
OUTPUT
DUT
R_L (NOTE)
500Ω
OUTPUT
LOAD
C_L
50pF
NOTE: For AC Series Only: When V_CC = 1.5V, R_L = 1kΩ.
CD54AC CD54ACT
Input Level
Input Switching Voltage, V_S
Output Switching Voltage, V_S
V_CC
0.5 V_CC
0.5 V_CC
3V
1.5V
0.5 V_CC
FIGURE 2. PROPAGATION DELAY TIMES
4