CD40175BMS Datasheet, PDF (4/8 Pages) Intersil Corporation – CMOS Quad ‘D’ Type Flip-Flop

Specifications CD40175BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V
Input Voltage Low
VIL VDD = 10V, VOH > 9V, VOL < 1V
Input Voltage High
VIH VDD = 10V, VOH > 9V, VOL < 1V
Propagation Delay
Clock to Q Output
Propagation Delay
Clear to Q Output
Transition Time
Minimum Data Setup
Time
Minimum Data Hold Time
Minimum Clear Pulse
Width
Maximum Clock Rise or
Fall Time
Minimum Clear Removal
Time (Clear to be High
before Positive Transition
of Clock)
Minimum Clock Pulse
Width
Input Capacitance
TPHL1
TPLH1
TPHL2
TTHL
TTLH
TS
TH
TW
TRCL
TFCL
TREM
TW
CIN
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Any Input
NOTES
1, 2
1, 2
1, 2
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE MIN
+125^oC
-
-55^oC
-
+25^oC, +125^oC,
-
-55^oC
+25^oC, +125^oC,
7
-55^oC
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
15
+25^oC
15
+25^oC
15
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
MAX
-2.4
-4.2
3
UNITS
mA
mA
V
-
V
160
ns
120
ns
200
ns
150
ns
100
ns
80
ns
120
ns
50
ns
40
ns
80
ns
40
ns
30
ns
200
ns
80
ns
60
ns
-
µs
-
µs
-
µs
250
ns
100
ns
80
ns
250
ns
100
ns
75
ns
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
7-1395