82C59A Datasheet, PDF (4/20 Pages) Intersil Corporation – CMOS Priority Interrupt Controller

82C59A
A more desirable method would be one that would allow the
microprocessor to be executing its main program and only
stop to service peripheral devices when it is told to do so by
the device itself. In effect, the method would provide an
external asynchronous input that would inform the processor
that it should complete whatever instruction that is currently
being executed and fetch a new routine that will service the
requesting device. Once this servicing is complete, however,
the processor would resume exactly where it left off.
This is the Interrupt-driven method. It is easy to see that sys-
tem throughput would drastically increase, and thus, more
tasks could be assumed by the microcomputer to further
enhance its cost effectiveness.
INT
CPU
The Programmable Interrupt Controller (PlC) functions as an
overall manager in an Interrupt-Driven system. It accepts
requests from the peripheral equipment, determines which
of the incoming requests is of the highest importance (prior-
ity), ascertains whether the incoming request has a higher
priority value than the level currently being serviced, and
issues an interrupt to the CPU based on this determination.
Each peripheral device or structure usually has a special
program or “routine” that is associated with its specific func-
tional or operational requirements; this is referred to as a
“service routine”. The PlC, after issuing an interrupt to the
CPU, must somehow input information into the CPU that can
“point” the Program Counter to the service routine associ-
ated with the requesting device. This “pointer” is an address
in a vectoring table and will often be referred to, in this docu-
ment, as vectoring data.
RAM
ROM
PIC
I/O (1)
I/O (2)
I/O (N)
FIGURE 3. INTERRUPT METHOD
82C59A Functional Description
The 82C59A is a device specifically designed for use in real
time, interrupt driven microcomputer systems. It manages
eight levels of requests and has built-in features for expand-
ability to other 82C59As (up to 64 levels). It is programmed
by system software as an I/O peripheral. A selection of prior-
ity modes is available to the programmer so that the manner
in which the requests are processed by the 82C59A can be
configured to match system requirements. The priority
modes can be changed or reconfigured dynamically at any
time during main program operation. This means that the
complete interrupt structure can be defined as required,
based on the total system environment.
Interrupt Request Register (IRR) and In-Service Register
(ISR)
The interrupts at the IR input lines are handled by two registers
in cascade, the Interrupt Request Register (lRR) and the In-
Service Register (lSR). The IRR is used to indicate all the inter-
rupt levels which are requesting service, and the ISR is used to
store all the interrupt levels which are currently being serviced.
D₇ - D₀
DATA
BUS
BUFFER
INTA
INT
CONTROL LOGIC
RD
WR
A₀
CS
CAS 0
CAS 1
CAS 2
SP/EN
READ/
WRITE
LOGIC
CASCADE
BUFFER
COMPARATOR
IN
SERVICE
REG
(ISR)
PRIORITY
RESOLVER
IR0
IR1
INTERRUPT
IR2
REQUEST
IR3
REG
IR4
(IRR)
IR5
IR6
IR7
INTERRUPT MASK REG
(IMR)
INTERNAL BUS
FIGURE 4. 82C59A FUNCTIONAL DIAGRAM
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