82C59A Datasheet, PDF (10/20 Pages) Intersil Corporation – CMOS Priority Interrupt Controller

82C59A
immediately before returning from the service routine, or if
the AEOI (Automatic End of Interrupt) bit is set, until the trail-
ing edge of the last INTA. While the IS bit is set, all further
interrupts of the same or lower priority are inhibited, while
higher levels will generate an interrupt (which will be
acknowledged only if the microprocessor internal interrupt
enable flip-flop has been re-enabled through software).
After the initialization sequence, IR0 has the highest priority
and IR7 the lowest. Priorities can be changed, as will be
explained in the rotating priority mode or via the set priority
command.
OCW1
A₀
D₇
D₆
D₅
1
M₇
M₆
M₅
D₄
D₃
M₄
M₃
D₂
D₁
D₀
M₂
M₁
M₀
OCW2
Interrupt Mask
1 = Mask set
0 = Mask reset
A₀
D₇
D₆
D₅
D₄
D₃
D₂
D₁
D₀
0
R
SL
EOI
0
0
L₂
L₁
L₀
0 01
0 11
1 01
1 00
0 00
1 11
1 10
0 10
OCW3
Non-specific EOI command
† Specific EOI command
Rotate on non-specific EOI command
Rotate in automatic EOI mode (set)
Rotate in automatic EOI mode (clear)
† Rotate on specific EOI command
† Set priority command
No operation
End of interrupt
Automatic rotation
Specific rotation
† L₀ - L₂ are used
IR LEVEL TO BE
ACTED UPON
0 123 4 567
0 101 0 101
0 011 0 011
0 000 1 111
A₀
D₇
D₆
D₅
D₄
D₃
D₂
D₁
D₀
0
0
ESMM SMM
0
1
P
RR
RIS
READ REGISTER COMMAND
01
0
1
00
1
1
Read IR reg on Read IS reg on
No Action ^{next RD pulse next RD pulse}
1 = Poll command
0 = No poll command
SPECIAL MASK MODE
01
0
1
00
1
1
Reset special Set special
No Action ^mask
mask
FIGURE 8. 82C59A OPERATION COMMAND WORD FORMAT
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