ISL5416 Datasheet, PDF (36/71 Pages) Intersil Corporation – Four-Channel Wideband Programmable DownConverter

ISL5416
Tables of I/O Registers
P(31:0)
TABLE 23. CHANNEL INPUT FORMAT (IWA = 0*00h) RESET STATE = 0x00000000h
FUNCTION
31:16 UNUSED.
15
FIXED GAIN MODE IN VGA.
14
RESERVED. Set to 1.
13
INVERT INPUT CLOCK.
1 = High -> Low edge of the input clock samples input data.
0 = Low -> High edge of the input clock samples input data.
12
INPUT CLOCK SOURCE.
1 = CLKC
0 = CLKA for Ain (address 0000 XXX1 0000 0000)
CLKB for Bin (address 0000 XX1X 0000 0000)
CLKD for Din (address 0000 1XXX 0000 0000)
CLKC is always used for Cin
The rising edge of CLKC is always used for the channel processing and output timing.
11
INPUT FORMAT.
1 = offset binary.
0 = 2’s complement
10
GATED & INTERPOLATED.
1 = input interpolated.
0 = input gated.
9:7
DEMUX DELAY.
000 = no delay, take sample aligned with the enable.
111 = take 7th sample after the enable.
6:5
RESERVED. Set to 0.
4
LSB TO MSB SWAP ON DATA.
1 = input bus reversed MSB for LSB -- XIN(0) = MSB.
0 = input bus normal XIN(16) = MSB
Provided to simplify circuit board routing.
3:2
FIXED/FLOATING POINT MODE.
00 = 16-bit fixed point (bits 16:1, 0 unused).
01 = 14/3 floating point (bits 16:3 mantissa, 2:0 exponent).
10 = 15/2 floating point (bits 16:2 mantissa, 1:0 exponent).
11 = 16/1 floating point (bits 16:1 mantissa, 0 exponent).
1:0
RESERVED. Set to 0.
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