ISL6322_14 Datasheet, PDF (35/41 Pages) Intersil Corporation – Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications

ISL6322
“Compensation with Load-line Regulation” on page 35 and
“Compensation without Load-line Regulation” on page 36.
COMPENSATION WITH LOAD-LINE REGULATION
The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R_C and C_C.
C₂ (OPTIONAL)
R_C ^CC
COMP
FB
ISL6322
IDROOP
R_FB
VDIFF
FIGURE 23. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6322 CIRCUIT
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage mode approximation,
yields a solution that is always stable with very close to ideal
transient performance.
Select a target bandwidth for the compensated system, f₀.
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f₀
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
In Equation 41:
- L is the per-channel filter inductance divided by the
number of active channels,
- C is the sum total of all output capacitors,
- ESR is the equivalent series resistance of the bulk output
filter capacitance, and
- V_PP is the peak-to-peak sawtooth signal amplitude as
described in the “Electrical Specifications” on page 7.
Once selected, the compensation values in Equation 41
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R_C. Slowly increase the
value of R_C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C_C will not need adjustment. Keep the value of C_C from the
case equations in Equation 41 unless some performance
issue is noted.
Case 1:
---------------1----------------
2⋅π⋅ L⋅C
>
f₀
R_C = R_FB ⋅ ^2-----â‹---^π-----^â‹---0f--⁰-.--6-^â‹--6-V----_â‹-^p--V-^p---_I-^â‹-_N-------L----^â‹---C---
C_C
=
--------------0---.--6---6-----^â‹---V----^I--^N----------------
2 ⋅ π ⋅ V_PP ⋅ R_FB ⋅ f₀
Case 2:
---------------1----------------
2⋅π⋅ L⋅C
≤
f₀
<
2-----⋅^---π^-----⋅^---C--1----⋅^{---E----S-----R---}
R_C
=
R_F
B
⋅
-V----^P----^P-----^â‹---⁽--2-----^â‹---^π----⁾--²----^â‹-----f-⁰--²-----^â‹---L-----^â‹---C---
0.66 ⋅ V_IN
C_C
=
------------------------------0----.-6----6-----^â‹---V----^I--^N--------------------------------
(2 ⋅ π)² ⋅ f₀₂ ⋅ V_PP ⋅ R_FB ⋅ L ⋅ C
(EQ. 41)
Case 3:
f₀
>
------------------1-------------------
2 ⋅ π ⋅ C ⋅ ESR
R_C
=
R_FB
⋅
-2-----^â‹---^π-----^â‹---f--⁰-----^â‹---V----^p---^p-----^â‹---L--
0.66 ⋅ V_IN ⋅ ESR
C_C
=
----0----.--6---6-----^â‹---V----^I--^N-----^â‹---E----S-----R------^â‹-------C-------
2 ⋅ π ⋅ V_PP ⋅ R_FB ⋅ f₀ ⋅ L
The optional capacitor C₂, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 23). Keep
a position available for C₂, and be prepared to install a
high-frequency capacitor of between 22pF and 150pF in
case any leading edge jitter problem is noted.
35
FN6328.2
August 2, 2007