ISL6322_14 Datasheet, PDF (32/41 Pages) Intersil Corporation – Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications

ISL6322
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I_M, V_D(ON), the switching
frequency, f_S, and the length of dead times, t_d1 and t_d2, at
the beginning and the end of the lower-MOSFET conduction
interval respectively.
PLOW_{, 2} = VD_(ON) ⋅ fS ⋅
⎜⎛^I--M---- ₊ ^I--P-----P--⎟⎞
⎝N 2 ⎠
⋅
td1
+ _{⎝⎜⎜⎛}^I--NM---- _– ^{I--P--2---P--}_{⎠⎟⎟⎞}
⋅
td2
(EQ. 24)
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of P_LOW,1 and P_LOW,2.
UPPER MOSFET POWER CALCULATION
In addition to r_DS(ON) losses, a large portion of the
upper-MOSFET losses are due to currents conducted
across the input voltage (V_IN) during switching. Since a
substantially higher portion of the upper-MOSFET losses are
dependent on switching frequency, the power calculation is
more complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times, the lower-MOSFET body-diode
reverse-recovery charge, Q_rr, and the upper MOSFET
r_DS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 25,
the required time for this commutation is t₁ and the
approximated associated power loss is P_UP,1.
P _{U P,1}
≈
V_IN
⋅
⎛
⎝
I--_M---
N
+
I--_{P-2---P--⎠⎞}
⋅
⎛
⎜
t--_1--
⎞
⎟
⎝ ²âŽ 
⋅
f_S
(EQ. 25)
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t₂. In Equation 26, the
approximate power loss is P_UP,2.
P_{UP, 2}
≈
V_IN
⋅
⎛
⎜
-I-^M---
⎝N
–
I--_{P----P--⎟⎞}
2_⎠
⋅
⎛
⎜
⎝
t--_2--
⎞
⎟
2_⎠
⋅
f_S
(EQ. 26)
A third component involves the lower MOSFET
reverse-recovery charge, Q_rr. Since the inductor current has
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Q_rr, it is
conducted through the upper MOSFET across VIN. The
power dissipated as a result is P_UP,3.
P_UP,3 = V_IN ⋅ Q_rr ⋅ f_S
(EQ. 27)
Finally, the resistive part of the upper MOSFET is given in
Equation 28 as P_UP,4.
P_UP,4 ≈ r_DS(ON) ⋅ d ⋅
⎛
⎜
⎝
-I-^M---⎟⎞
N⎠
2
+
-I-^P----^P--²-
12
(EQ. 28)
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results from
Equations 25, 26, 27 and 28. Since the power equations
depend on MOSFET parameters, choosing the correct
MOSFETs can be an iterative process involving repetitive
solutions to the loss equations for different MOSFETs and
different switching frequencies.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three drivers
in the controller package, the total power dissipated by all three
drivers must be less than the maximum allowable power
dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W at
room temperature. See “Layout Considerations” on page 38 for
thermal transfer improvement suggestions.
When designing the ISL6322 into an application, it is
recommended that the following calculation is used to ensure
safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses, P_{Qg_TOT}, due to
the gate charge of MOSFETs and the integrated driver’s
internal circuitry and their corresponding average driver current
can be estimated with Equations 29 and 30, respectively.
P_{Qg_TOT} = P_{Qg_Q1} + P_{Qg_Q2} + I_Q ⋅ VCC
(EQ. 29)
P _{Q g _Q1}
=
3_--
2
⋅
Q_G
1
⋅
PV
C
C
⋅
F_S
W
⋅
N_Q1
⋅
N_PHA
S
E
P_{Qg_Q2} = Q_G2 ⋅ PVCC ⋅ F_SW ⋅ N_Q2 ⋅ N_PHASE
I_DR
=
⎛
⎝
3_--
2
⋅
Q_G1
⋅
N
Q
1
+
Q_G
2
⋅
N_Q
⎞
2⎠
⋅ N_PHASE ⋅ F_SW + I_Q
(EQ. 30)
In Equations 29 and 30, P_{Qg_Q1} is the total upper gate drive
power loss and P_{Qg_Q2} is the total lower gate drive power loss;
the gate charge (Q_G1 and Q_G2) is defined at the particular gate
to source drive voltage PVCC in the corresponding MOSFET
data sheet; I_Q is the driver total quiescent current with no load
at both drive outputs; N_Q1 and N_Q2 are the number of upper
and lower MOSFETs per phase, respectively; N_PHASE is the
number of active phases. The I_Q*VCC product is the quiescent
power of the controller without capacitive load and is typically
75mW at 300kHz.
32
FN6328.2
August 2, 2007