HSP50216_15 Datasheet, PDF (35/59 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

HSP50216
P(31:0)
28:24
23
22
21:20
19
18
17
16
15
14
13:12
11:0
TABLE 13. FILTER COMPUTE ENGINE/RESAMPLER CONTROL REGISTER (IWA = *00Ah) (Continued)
FUNCTION
μPZ(4:0). These bits, when set to zero, zero the corresponding read pointer address bits. This allows the pointers to be aliased, i.e.,
multiple filters can access and/or modify the same pointer. They are provided to change filters, coefficients or decimation over a
sequence.
Unused, set to 0.
Timing (resampler) NCO ENsync. If this bit is set, the center frequency is updated on a SYNCI. Set to 1.
RSRVRS(1:0). Set to 01.
Beginning/End. This bit selects whether the resampler NCO is updated at the beginning of a FIR computation or at the end of each
FIR output computation. Usually, the resampler will be updated once at the beginning of each resampler computation and this will be
bit set to 1.
1
Once at the beginning of the FIR instruction.
0
At the last tap of each of the instruction’s FIR computations (once per output).
RSModeSelect. This bit selects whether the resampler is a phase shifter or a frequency shifter.
0 Phase shift. It uses the top 5-bits of the timing NCO frequency to determine a phase shift and disables feedback in the timing
NCO phase accumulator -- effect of the resampler is a constant phase shift.
1 Frequency shift. effect of the resampler is a change in the sample rate.
RSCO. This bit is provided to force the resampler NCO carry when using the resampler as a phase shifter rather than for a frequency
shift. This bit must be set for phase shifting and cleared for frequency shifting. (The bit is Or-ed with the normal carry.)
RS NCO clear phase accumulator feedback on load. When this bit is set, the feedback in the resampler NCO phase accumulator is
zeroed whenever the center frequency word is updated. This forces the NCO to a known phase so the phase of multiple channels
can be aligned.
Force NCO load. This bit, when set, zeroes the feedback in the resampler NCO phase accumulator. This is provided for test or to
use the resampler for phase instead of frequency shifting.
Enable RS freq offset. This bit, when set, enables the serially loaded resampler offset frequency word. When zero, the offset is
zeroed. To disable the shifting, see IWA register *000h.
Serial input word size. These bits select the number of bits in the resampler offset frequency word (loaded serially via
SOF/SOFSYNC).
00 8 bits
01 16 bits
10 24 bits
11 32 bits
FIFODelay. A FIFO is provided at the output of the filter compute engine to smooth the sample spacing when using the resampler or
interpolation FIRs. In these filters, the outputs can be produced in bursts or with gaps. The FIFO takes the samples in and outputs
them based on a counter timeout. If the FIFO is empty and the counter is at its terminal count (hold state), the data is passed through
and the counter is reloaded. If the counter is not at terminal count, the data is held in the FIFO until the counter times out. The FIFO
can hold up to 4 samples. The delay is programmed in clock periods. The value programmed is one less than the number of clocks
of delay. Set to 0 for a delay of one (fall through). The delay should be programmed to slightly less than the desired spacing to prevent
overflow.
P(15:0)
13:9
8:0
TABLE 14. FILTER START OFFSET REGISTER (IWA = *00Bh)
FUNCTION
RAM Instruction number to which the offset is applied. 0-31. Aliasing applies. Used for polyphase filters.
Amount of offset. Offsets the data RAM address for filter #n. This is used to offset the channels from each other when breaking the
processing up among multiple channels for polyphase filters. For example, four channels can receive the same data at 8 MSPS, filter
and decimate by 8 to output at 1MHz. If the computations are offset by 2 samples each, then the outputs of the four channels can be
multiplexed together to get an output sample rate of 4MSPS. With a 64MSPS clock, the composite filter could have more than 100
taps where a single channel would only be capable of around 24 taps at a 4MHz output.
EXCEPT IN VERY RARE CIRCUMSTANCES, THIS VALUE SHOULD BE A NEGATIVE NUMBER.
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FN4557.8
October 5, 2015