X9251 Datasheet, PDF (3/22 Pages) Xicor Inc. – Quad Digitally-Controlled (XDCP) Potentiometer

X9251
CIRCUIT LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage ampli-
fier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
• Control the gain in audio and home entertainment
systems
• Provide the variable DC bias for tuners in RF wire-
less systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
PIN CONFIGURATION
SO
A0
R_W3
R_H3
R_L3
NC
V_CC
R_L0
R_H0
R_W0
CS
WP
SOIC/TSSOP
1
24
2
23
3
22
4
21
5
20
6
19
X9251
7
18
8
17
9
16
10
15
11
14
12
13
HOLD
SCK
R_L2
R_H2
R_W2
NC
V_SS
R_W1
R_H1
R_L1
A1
SI
PIN ASSIGNMENTS
Pin
(SOIC)
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
20
21
22
23
24
6, 19
Symbol
Function
SO Serial Data Output for SPI bus
A0 Device Address for SPI bus. (See Note 1)
R_W3
R_H3
R_L3
V_CC
R_L0
R_H0
R_W0
CS
Wiper Terminal of DCP3
High Terminal of DCP3
Low Terminal of DCP3
System Supply Voltage
Low Terminal of DCP0
High Terminal of DCP0
Wiper Terminal of DCP0
SPI bus. Chip Select active low input
WP Hardware Write Protect - active low
SI Serial Data Input for SPI bus
A1 Device Address for SPI bus. (See Note 1)
R_L1
R_H1
R_W1
V_SS
R_W2
R_H2
R_L2
SCK
Low Terminal of DCP1
High Terminal of DCP1
Wiper Terminal of DCP1
System Ground
Wiper Terminal of DCP2
High Terminal of DCP2
Low Terminal of DCP2
Serial Clock for SPI bus
HOLD Device select. Pauses the SPI serial bus.
NC No Connect
Note 1: A0 - A1 device address pins must be tied to a logic level.
3
FN8166.2
September 14, 2005