X1286V14T1 Datasheet, PDF (3/25 Pages) Intersil Corporation – Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM

X1286
PIN ASSIGNMENTS
Pin Number
EIAJ SOIC TSSOP
1
1
2
2
3
6
4
7
5
8
6
9
7
13
8
14
Symbol
X1
X2
PHZ/IRQ
V_SS
SDA
SCL
V_BACK
V_CC
Brief Description
X1. The X1 pin is the input of an inverting amplifier. An external 32.768kHz quartz
crystal is used with the X1286 to supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation
circuitry is included to form a complete oscillator circuit. Care should be taken in the
placement of the crystal and the layout of the circuit. Plenty of ground plane around
the device and short traces to X1 are highly recommended. See Application section
for more recommendations.
X2. The X2 pin is the output of an inverting amplifier. An external 32.768kHz
quartz crystal is used with the X1286 to supply a timebase for the real time clock.
The recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation
circuitry is included to form a complete oscillator circuit. Care should be taken in the
placement of the crystal and the layout of the circuit. Plenty of ground plane around
the device and short traces to X2 are highly recommended. See Application section
for more recommendations.
Programmable Frequency/Interrupt Output – PHZ/IRQ. This is either an
output from the internal oscillator or an interrupt signal output. It is a CMOS
output.
When used as frequency output, this signal has a frequency of 32.768kHz,
100Hz, 1Hz or inactive.
When used as interrupt output, this signal notifies a host processor that an alarm
has occurred and an action is required. It is an active LOW output.
The control bits for this function are FO1 and FO0 and are found in address
0011h of the Clock Control Memory map. See “Programmable Frequency Output
Bits—FO1, FO0” on page 13.
V_SS.
Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out
of the device. It has an open drain output and may be wire ORed with other open
drain or open collector outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up resistor. The output circuitry
controls the fall time of the output signal with the use of a slope controlled pull-
down. The circuit is designed for 400kHz 2-wire interface speed.
Serial Clock (SCL). The SCL input is used to clock all data into and out of the
device. The input buffer on this pin is always active (not gated).
V_BACK. This input provides a backup supply voltage to the device. V_BACK
supplies power to the device in the event the V_CC supply fails. This pin can be
connected to a battery, a Supercap or tied to ground if not used.
V_CC.
3
FN8101.1
April 14, 2006