X1286V14T1 Datasheet, PDF (18/25 Pages) Intersil Corporation – Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM

X1286
Acknowledge Polling
Disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
X1286 initiates the internal nonvolatile write cycle.
Acknowledge polling can begin immediately. To do
this, the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If the
X1286 is still busy with the nonvolatile write cycle then
no ACK will be returned. When the X1286 has com-
pleted the write operation, an ACK is returned and the
host can proceed with the read or write operation.
Refer to the flow chart in Figure 12.
Read Operations
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
Current Address Read
Internally the X1286 contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the sixteen bit
address is initialized to 0h. In this way, a current
address read immediately after the power-onpower-on
reset can download the entire contents of memory
starting at the first location.Upon receipt of the Slave
Address Byte with the R/W bit set to one, the X1286
issues an acknowledge, then transmits eight data bits.
The master terminates the read operation by not
responding with an acknowledge during the ninth
clock and issuing a stop condition. Refer to Figure 11
for the address, acknowledge, and data transfer
sequence.
Figure 12. Acknowledge Polling Sequence
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Slave
Address Byte
(Read or Write)
Issue STOP
NO
ACK
returned?
YES
nonvolatile write
NO
Cycle complete. Continue
command sequence?
Issue STOP
YES
Continue normal
Read or Write
command
sequence
PROCEED
Figure 11. Current Address Read Sequence
S
Signals from
t
a
Slave
S
t
the Master
r Address
o
t
p
SDA Bus
1
1 1 11
Signals from
the Slave
A
C
Data
K
18
FN8101.1
April 14, 2006