ISL78302A_14 Datasheet, PDF (3/11 Pages) Intersil Corporation – Dual LDO with Low Noise, Very High PSRR and Low IQ

Pin Configuration
ISL78302A
ISL78302A
(10 LD 3X3 DFN)
TOP VIEW
VIN 1
EN1 2
EN2 3
CBYP 4
CPOR 5
10 VO1
9 VO2
8 _POR2
7 POR1
6 GND
Pin Descriptions
PIN NUMBER PIN NAME
TYPE
DESCRIPTION
1
VIN
Analog I/O
Supply Voltage/LDO Input. Connect a 1µF capacitor to GND.
2
EN1 Low Voltage Compatible CMOS Input LDO-1 Enable
3
EN2 Low Voltage Compatible CMOS Input LDO-2 Enable
4
CBYP
Analog I/O
Reference Bypass Capacitor Pin. Optionally connect capacitor of value 0.01µF to 1µF
between this pin and GND to tune in the desired noise and PSRR performance.
5
CPOR
Analog I/O
POR2 Delay Setting Capacitor Pin. Connect a capacitor between this pin and GND to
delay the POR2 output release after LDO-2 output reaches 94% of its specified
voltage level (200ms delay per 0.01µF).
6
GND
Ground
Connection to system ground. Connect to PCB Ground plane.
7
POR1
Open Drain Output (1mA)
Open-drain POR Output for LDO-1 (active-low). Internally connected to VO1 through
100kΩ resistor.
8
POR2
Open Drain Output (1mA)
Open-drain POR Output for LDO-2 (active-low). Internally connected to VO2 through
100kΩ resistor.
9
VO2
Analog I/O
LDO-2 Output. Connect capacitor of value 1µF to 10µF to GND
(1µF recommended).
10
VO1
Analog I/O
LDO-1 Output. Connect capacitor of value 1µF to 10µF to GND
(1µF recommended).
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
VO1 VOLTAGE
(V)
VO2 VOLTAGE
(V)
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG DWG. #
ISL78302AARMMZ DNAL
3.0
3.0
-40 to +105 10 Ld 3x3 DFN
L10.3x3C
ISL78302AARLLZ
DNAM
2.9
2.9
-40 to +105 10 Ld 3x3 DFN
L10.3x3C
ISL78302AARJMZ
DNAN
2.8
3.0
-40 to +105 10 Ld 3x3 DFN
L10.3x3C
ISL78302AARJRZ
DNAP
2.8
2.6
-40 to +105 10 Ld 3x3 DFN
L10.3x3C
ISL78302AARJCZ
DNAK
2.8
1.8
-40 to +105 10 Ld 3x3 DFN
L10.3x3C
ISL78302AARGCZ
DNAR
2.7
1.8
-40 to +105 10 Ld 3x3 DFN
L10.3x3C
ISL78302AARPLZ
DNAS
1.85
2.9
-40 to +105 10 Ld 3x3 DFN
L10.3x3C
ISL78302AARBJZ
DNAT
1.5
2.8
-40 to +105 10 Ld 3x3 DFN
L10.3x3C
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78302A. For more information on MSL, please see Tech Brief TB363.
3
FN7932.1
December 23, 2013