ISL6115_07 Datasheet, PDF (3/12 Pages) Intersil Corporation – Power Distribution Controllers

ISL6115, ISL6116, ISL6117, ISL6120
Simplified Block Diagram
I_SET
I_SEN
GATE
V_SS
10µA
18V
UV
-
+
+
V_REF
-
V_DD
+
-
+
POR
8V
-
QN ^R
R
QS
ENABLE
12V
ISL611X
UV DISABLE
OC ₊
-
7.5K
CLIM
FALLING
EDGE
DELAY
ENABLE
-
+
WOCLIM
20µA
18V
20µA
+
-
+
1.86V
-
RISING
EDGE
PULSE
PWRON
PGOOD
CTIM
V_DD
Pin Descriptions
PIN #
1
SYMBOL
ISET
FUNCTION
Current Set
DESCRIPTION
Connect to the low side of the current sense resistor through the current limiting set resistor. This
pin functions as the current limit programming pin.
2
ISEN
Current Sense
Connect to the more positive end of sense resistor to measure the voltage drop across this
resistor.
3
GATE
External FET Gate Drive Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground
Pin
sets the turn-on ramp. At turn-on this capacitor will be charged to V_DD +5V (ISL6115) and to
V_DD (ISL6116, ISL6117, ISL6120) by a 10μA current source.
4
VSS
Chip Return
5
V_DD
Chip Supply
12V chip supply. This can be either connected directly to the +12V rail supplying the switched
load voltage or to a dedicated V_SS +12V supply.
6
CTIM
Current Limit Timing
Connect a capacitor from this pin to ground. This capacitor determines the time delay
Capacitor
between an overcurrent event and chip output shutdown (current limit time-out). The duration
of current limit time-out is equal to 93kΩ x C_TIM.
7
PGOOD Power Good Indicator
Indicates that the voltage on the ISEN pin is satisfactory. PGOOD is driven by an open drain
N-Channel MOSFET and is pulled low when the output voltage (VISEN) is less than the UV
level for the particular IC.
8
PWRON Power ON
PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is driven
high to a maximum of 5V or is left open. After a current limit time out, the chip is reset by a
low level signal applied to this pin. This input has 20μA pull up capability.
3
February 6, 2007