ISL6115_07 Datasheet, PDF (10/12 Pages) Intersil Corporation – Power Distribution Controllers

ISL6115, ISL6116, ISL6117, ISL6120
Typical Performance Curves (Continued)
+350V
VDRAIN 50V/DIV
IOUT 1A/DIV
+350V
VDRAIN 50V/DIV
IOUT 1A/DIV
VGATE 5V/DIV
PWRON 5V/DIV
0V
2ms/DIV
FIGURE 19. +350V LOW SIDE SWITCHING CGATE = 100pF
ISL6115EVAL1 Board
The ISL6115EVAL1 is configured as a +12V high side switch
controller with the CR level set at ~1.5A. (See Figure 21 for
ISL6115EVAL1 schematic and Table 4 for BOM). Bias and
load connection points are provided along with test points for
each IC pin.
With the chip to be biased from the +12V bus being
switched, through B2, GND B5, the load connected between
B3 and B4 and with jumper J1 installed the ISL6115 can be
evaluated. PWRON pin pulls high enabling the ISL6115 if not
driven low.
With R2 = 750Ω the CR Vth is set to 15mV and with the
10mΩ sense resistor the ISL6115EVAL1 has a nominal CR
level of 1.5A. The 0.047μF delay time to latch-off capacitors
results in a nominal 4.4ms before latch-off of outputs after an
OC event.
Also included with the ISL6115EVAL1 board are one each of
the ISL6116, ISL6117 and ISL6120 for evaluation.
VGATE 5V/DIV.
PWRON 5V/DIV
0V
2ms/DIV
FIGURE 20. +350V LOW SIDE SWITCHING CGATE = 1000pF
ISL6116EVAL1 Board
The ISL6116EVAL1 is default configured as a negative
voltage low side switch controller with a ~2.4A CR level.
(See Figure 22 for ISL6116EVAL1 schematic and Table 4 for
BOM and component description). This basic configuration
is capable of controlling both larger positive or negative
potential voltages with minimal changes.
Bias and load connection points are provided in addition to
test points, TP1-8 for each IC pin. The terminals, J1 and J4
are for the bus voltage and return, respectively, with the
more negative potential being connected to J4. With the load
between terminals J2 and J3 the board is now configured for
evaluation. The device is enabled through LOGIN, TP9 with
a TTL signal. ISL6116EVAL1 includes a level shifting circuit
with an opto-coupling device for the PWRON input so that
standard TTL logic can be translated to the -V reference for
chip control.
When controlling a positive voltage, PWRON can be
accessed at TP8.
The ISL6116EVAL1 is provided with a high voltage linear
regulator for convenience to provide chip bias from ±24V to
±350V. This can be removed and replaced with the zener &
resistor bias scheme as discussed earlier. High voltage
regulators and power discrete devices are no longer
available from Intersil but can be purchased from other
semiconductor manufacturers.
Reconfiguring the ISL6116EVAL1 board for a higher CR
level can be done by changing the R_SENSE and R_ISET
resistor values as the provided FET is 75A rated. If
evaluation at >60V, an alternate FET must be chosen with
an adequate BV_DSS.
10
February 6, 2007