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ISL22343_15 Datasheet, PDF (3/19 Pages) Intersil Corporation – Low Noise, Low Power, I2C Bus, 256 Taps | |||
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ISL22343
Pin Descriptions
TSSOP PIN
QFN PIN
SYMBOL
DESCRIPTION
1
19
RH3
âHighâ terminal of DCP3
2
20
RL3
âLowâ terminal of DCP3
3
1
RW3
âWiperâ terminal of DCP3
4
2
A2
Device address input for the I2C interface
5
3
SCL
Open drain I2C interface clock input
6
4
SDA
Open drain Serial data I/O for the I2C interface
7
5
GND
Device ground pin
8
6
RW2
âWiperâ terminal of DCP2
9
7
RL2
âLowâ terminal of DCP2
10
8
RH2
âHighâ terminal of DCP2
11
9
RW1
âWiperâ terminal of DCP1
12
10
RL1
âLowâ terminal of DCP1
13
11
RH1
âHighâ terminal of DCP1
14
12
A0
Device address input for the I2C interface
15
13
A1
Device address input for the I2C interface
16
14
VCC
Positive power supply pin
17
15
V-
Negative power supply pin
18
16
RH0
âHighâ terminal of DCP0
19
17
RL0
âLowâ terminal of DCP0
20
18
RW0
âWiperâ terminal of DCP0
EPAD*
Exposed Die Pad internally connected to V-
NOTE: *PCB thermal land for QFN EPAD should be connected to V- plane or left floating. For more information refer to
http://www.intersil.com/data/tb/TB389.pdf
3
FN6423.2
August 17, 2015
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