ISL22343_15 Datasheet, PDF (12/19 Pages) Intersil Corporation – Low Noise, Low Power, I2C Bus, 256 Taps

ISL22343
Typical Performance Curves (Continued)
CS
SCL
WIPER
WIPER UNLOADED,
MOVEMENT FROM 0h to FFh
FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h
Pin Description
Potentiometers Pins
RHI AND RLI
The high (RHi) and low (RLi) terminals of the ISL22343 are
equivalent to the fixed terminals of a mechanical
potentiometer. RHi and RLi are referenced to the relative
position of the wiper and not the voltage potential on the
terminals. With WRi set to 255 decimal, the wiper will be
closest to RHi, and with the WRi set to 0, the wiper is closest
to RLi.
RWI
RWi is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WRi register.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for I²C
interface. It receives device address, operation code, wiper
address and data from an I²C external master device at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock.
SDA requires an external pull-up resistor, since it is an open
drain input/output.
SERIAL CLOCK (SCL)
This input is the serial clock of the I²C serial interface. SCL
requires an external pull-up resistor, since it is an open drain
input.
DEVICE ADDRESS (A2, A1, A0)
The address inputs are used to set three least significant bits
of the 7-bit I²C interface slave address. A match in the slave
address serial data stream must match with the Address
input pins in order to initiate communication with the
12
FIGURE 14. LARGE SIGNAL SETTLING TIME
ISL22343. A maximum of eight ISL22343 devices may
occupy the I²C serial bus (See Table 3).
Principles of Operation
The ISL22343 is an integrated circuit incorporating four
DCPs with its associated registers, non-volatile memory and
an I²C serial interface providing direct communication
between a host and the potentiometer and memory. The
resistor arrays are comprised of individual resistors
connected in a series. At either end of the array and
between each resistor is an electronic switch that transfers
the potential at that point to the wiper.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
When the device is powered down, the last value stored in
IVRi will be maintained in the non-volatile memory. When
power is restored, the contents of the IVRi are recalled and
loaded into the corresponding WRi to set the wipers to their
initial positions.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RHi and RLi pins). The RWi pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WRi). When the WRi of a DCP
contains all zeroes (WRi[7:0]= 00h), its wiper terminal (RWi)
is closest to its “Low” terminal (RLi). When the WRi register
of a DCP contains all ones (WRi[7:0] = FFh), its wiper
terminal (RWi) is closest to its “High” terminal (RHi). As the
value of the WRi increases from all zeroes (0) to all ones
(255 decimal), the wiper moves monotonically from the
position closest to RLi to the position closest to RHi. At the
FN6423.2
August 17, 2015