ICL7135_14 Datasheet, PDF (3/15 Pages) Intersil Corporation – 41/2 Digit, BCD Output, A/D Converter

ICL7135
Absolute Maximum Ratings
Supply Voltage V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V
V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -9V
Analog Input Voltage (Either Input) (Note 1) . . . . . . . . . . . . V+ to V-
Reference Input Voltage (Either Input) . . . . . . . . . . . . . . . . V+ to V-
Clock Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V+
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . 0^oC to +70^oC
Thermal Information
Thermal Resistance (Typical, Note 2) . . . . . . . . . . . . . θ_JA (^oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+150^oC
Maximum Storage Temperature Range . . . . . . . . -65^oC to +150^oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . .+300^oC
NOTE: Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Input voltages may exceed the supply voltages provided the input current is limited to +100μA.
2. θ_JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications V+ = +5V, V- = -5V, T_A = +25^oC, f_CLK Set for 3 Readings/s, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
ANALOG (Notes 3, 4)
Zero Input Reading
Ratiometric Error (Note 4)
Linearity Over ± Full Scale (Error of Reading from Best Straight Line)
Differential Linearity (Difference Between Worse Case Step of
Adjacent Counts and Ideal Step)
V_lN = 0V, V_REF = 1.000V
V_lN = V_REF = 1.000V
-2V ≤ V_IN ≤ +2V
-2V ≤ V_IN ≤ +2V
Rollover Error (Difference in Reading for Equal Positive and
Negative Voltage Near Full Scale)
-V_lN ≡ +V_lN ≈ 2V
Noise (Peak-to-Peak Value Not Exceeded 95% of Time), e_N
Input Leakage Current, I_ILK
Zero Reading Drift (Note 7)
Scale Factor Temperature Coefficient, T_C (Notes 5 and 7)
V_lN = 0V, Full scale = 2.000V
V_lN = 0V
V_lN = 0V, 0^oC to +70^oC
VEx_lNt. =R+e2f.V0,p0p^o_mC/otoC +70^oC
DIGITAL INPUTS
Clock In, Run/Hold (See Figure 2)
DIGITAL OUTPUTS
V_INH
V_INL
I_INL
I_INH
V_IN = 0V
V_IN = +5V
MIN
TYP MAX UNITS
-00000
-3
-
-
+00000
0
0.5
0.01
+00000
+3
1
-
Counts
Counts
LSB
LSB
-
0.5
1
LSB
-
15
-
μV
-
1
10
pA
-
0.5
2
μV/^oC
-
2
5
ppm/×^oC
2.8
2.2
-
V
-
1.6
0.8
V
-
0.02
0.1
mA
-
0.1
10
μA
All Outputs, V_OL
B1, B2, B4, B8, D1, D2, D3, D4, D5, V_OH
BUSY, STROBE, OVERRANGE, UNDERRANGE, POLARITY, V_OH
SUPPLY
I_OL = 1.6mA
I_OH = -1mA
I_OH = -10μA
-
0.25 0.40
V
2.4
4.2
-
V
4.9
4.99
-
V
+5V Supply Range, V+
+4
+5
+6
V
-5V Supply Range, V-
-3
-5
-8
V
+5V Supply Current, I+
-5V Supply Current, I-
Power Dissipation Capacitance, C_PD
CLOCK
f_C = 0
f_C = 0
vs Clock Frequency
-
1.1
3.0
mA
-
0.8
3.0
mA
-
40
-
pF
Clock Frequency (Note 6)
DC
2000 1200
kHz
NOTES:
3. Tested in 4¹/₂ digit (20.000 count) circuit shown in Figure 3. (Clock frequency 120kHz.)
4. Tested with a low dielectric absorption integrating capacitor, the 27Ω INT OUT resistor shorted, and R_lNT = 0. See Component Value Selection Discussion.
5. The temperature range can be extended to +70^oC and beyond as long as the auto-zero and reference capacitors are increased to absorb the higher
leakage of the ICL7135.
6. This specification relates to the clock frequency range over which the lCL7135 will correctly perform its various functions See “Max Clock Frequency”
section for limitations on the clock frequency range in a system.
7. Parameter guaranteed by design or characterization. Not production tested.
3
FN3093.4