HS-80C85RH_02 Datasheet, PDF (3/16 Pages) Intersil Corporation – Radiation Hardened 8-Bit CMOS Microprocessor

HS-80C85RH
Pin Description
SYMBOL
PIN
NUMBER
A8 - A15
21-28
AD0-7
12-19
ALE
32
S0, S1, and
IO/M
31, 35,
and 36
RD
34
WR
33
READY
35
HOLD
39
HLDA
38
INTR
10
TYPE
DESCRIPTION
O Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/O address,
three-stated during Hold and Halt modes and during RESET.
I/O Multiplexed Address/Data Bus: Lower 8 bits of the memory address (or I/O address) appear on the bus
during the first clock cycle (T state) of a machine cycle. It then becomes the data bus during the second
and third clock cycles.
O Address Latch Enable: It occurs during the first clock state of a machine cycle and enables the address
to get latched into the on-chip latch of peripherals. The falling edge of ALE is set to guarantee setup and
hold times for the address information. The falling edge of ALE can also be used to strobe the status
information. ALE is never three-stated.
O Machine Cycle Status:
IO/M
S1
S0 STATUS
0
0
1 Memory write
0
1
0 Memory write
1
0
1 I/O write
1
1
0 I/O read
0
1
1 Opcode fetch
1
1
1 Opcode fetch
1
1
1 Interrupt acknowledge
T
0
0 Halt
T
X
X Hold
T
X
X Reset
T = three-State (high impedance)
X = Unspecified
S1 can be used as an advanced R/W status. IO/M, S0 and S1 become valid at the beginning of a machine
cycle and remain stable throughout the cycle. The falling edge of ALE may be used to latch the state of
these lines.
O Read Control: A low level on RD indicates the selected memory or I/O device is to be read and that the
Data Bus is available for the data transfer, three-stated during Hold and Halt modes and during RESET.
O Write Control: A low level on WR indicates the data on the Data Bus is to be written into the selected
memory or I/O location. Data is set up at the trailing edge of WR, three-stated during Hold and Halt modes
and during RESET.
I Ready: If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready
to send or receive data. If READY is low, the CPU will wait an integral number of clock cycles for READY
to go high before completing the read or write cycle. READY must conform to specified setup and hold
times.
I Hold: Indicates that another master is requesting the use of the address and data buses. The CPU, upon
receiving the hold request, will relinquish the use of the bus as soon as the completion of the current bus
transfer. Internal processing can continue. The processor can regain the bus only after the HOLD is
removed. When the HOLD is acknowledged, the Address, Data Bus, RD, WR, and IO/M lines are
3-stated.
O Hold Acknowledge: Indicates that the CPU has received the HOLD request and that it will relinquish the
bus in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the bus
one half clock cycle after HLDA goes low.
I Interrupt Request: Is used as a general purpose interrupt. It is sampled only during the next to the last
clock cycle of an instruction and during Hold and Halt states. If it is active, the Program Counter (PC) will
be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL
instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by
software. It is disabled by Reset and immediately after an interrupt is accepted.
3