HIP5060 Datasheet, PDF (3/6 Pages) Intersil Corporation – Power Control IC Single Chip PowerSupply

HIP5060
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V+. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V
DMOS Drain Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V
DMOS Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20A
DC Logic Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Output Voltage, Logic Outputs . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Input Voltage, Analog and Logic. . . . . . . . . . . . . . . . . . -0.3V to 16V
Operating Junction Temperature Range . . . . . . . . . .0^oC to +110^oC
Storage Temperature Range . . . . . . . . . . . . . . . . . -55^oC to +150^oC
Thermal Resistance
θ_JC
(Solder Mounted to . . . . . . . . . . . . . . . . . . . . . . . . . 3^oC/W Max
0.050” Thick Copper Heat Sink)
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +110^oC
(Controlled By Thermal Shutdown Circuit)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications V+ = 36V, T_J = 0^oC to +110^oC; Unless Otherwise Specified
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
DEVICE PARAMETERS
I+
Supply Current
PSEN = 12V
-
V_DDA
Internal Regulator Output
Voltage
V+ = 15V to 45V, I_OUT = 10mA
11.0
VINP
Reference Voltage
R_VINP
VINP Resistance
ERROR AMPLIFIERS
I_VINP = 0mA
VINP = 0
5.01
-
|V_IO|
Input Offset Voltage
I_VCMP = 0mA
-
(VREG - VINP)
R_IN VREG
g_m (VREG)
g_m (SFST)
I_VCMP
I_VCMP
OVTH
Input Resistance to GND
VREG Transconductance
I_VCMP/(VREG - VINP)
SFST Transconductance
I_VCMP/(VREG - SFST)
Maximum Source Current
Maximum Sink Current
Over-Voltage Threshold
VREG = 5.1V
-
VCMP = 1V to 8V, SFST = 11V
15
V_SFST < 4.9V
0.8
VREG = 4.95V, VCMP = 8V
-2.5
VREG = 5.25V, VCMP = 0.4V
0.75
Voltage at VREG for FLTN to be
6.2
latched
CLOCK
fq
Internal Clock Frequency
SLCT = 0V, V_DDD = 12V
0.9
V_TH CKIN External Clock Input Threshold SLCT = 12V
33
Voltages
DMOS TRANSISTORS
r_DS(on)
Drain-Source On-State
I Drain = 5A, T_J = +25^oC
-
Resistance
I_DSS
Drain-Source Leakage Current Drain to Source Voltage = 60V
-
CURRENT CONTROLLED PWM
|V_IO| VCMP Buffer Offset Voltage (VCMP - IRFO = 0mA to -5mA,
-
V_IRFO)
VCMP = 0.2V to 7.6V
V_TH IRFO Voltage at IRFO that disables
100
PWM. This is due to low load
current
TYP
19.5
-
5.1
900
-
56
30
-
-
-
-
1.0
-
-
1
-
-
MAX
UNITS
32
mA
13.2
V
5.19
V
-
Ω
10
mV
-
kΩ
50
mS
6
mS
-0.75
mA
2.5
mA
6.7
V
1.1
MHz
66
%V_DDD
0.13
Ω
100
µA
125
mV
270
mV
3