HA456_06 Datasheet, PDF (3/13 Pages) Intersil Corporation – 120MHz, Low Power, 8x8 Video Crosspoint Switch

HA456
Pin Descriptions
NAME
FUNCTION
NC
No connect. Not internally connected.
D1/ SER OUT Parallel Data Bit input D1 for Parallel Programming Mode. Serial Data Output (MSB of shift register) for cascading multiple
HA456s in serial programming mode. Simply connect Serial Data Out of one HA456 to Serial Data In of another HA456 to daisy
chain multiple devices.
D0/SER IN Parallel Data Bit Input D0 for Parallel Programming Mode. Serial Data Input (input to shift register) for serial programming mode.
A2, A1, A0 Output Channel Address Bits. These inputs select the output being programmed in parallel programming mode.
IN0-IN7
Analog Video Input Lines.
DGND
Digital Ground. Connect both DGND pins to AGND.
EDGE/LEVEL
A user strapped input that defines whether synchronous channel switching is edge or level controlled. With this pin strapped
high, the slave register loads from the master register (thus changing the switch matrix state) on the rising edge of the LATCH
signal. If it is strapped low (level mode), the slave register is transparent while LATCH is low, passing data directly from the
master register to the switch state decoders. Strapping EDGE/LEVEL and LATCH low causes the channel switch to execute on
the WR rising edge (not recommended for serial mode operation).
V+
Positive Supply Voltage. Connect all V+ pins together and decouple each pin to AGND (Figure 2).
SER/PAR
A user strapped input that defines whether the serial (SER/PAR = 1) or parallel (SER/PAR = 0) digital programming interface is
being utilized.
V-
Negative Supply Voltage. Connect both V- pins together and decouple each pin to AGND (Figure 2).
WR
LATCH
CE
CE
OUT7-OUT0
AGND
WRITE Input. In serial mode, data shifts into the shift register (Master Register) LSB from SER IN on the WR rising edge. In
parallel mode, the Master Register loads with D3:0 (if D3:0 = 0000 through 1000), or the appropriate action is taken (iff
D3:0=1011 through 1111), on the WR rising edge (see Table 1).
Synchronous Channel Switch Control Input. If EDGE/LEVEL = 1, data is loaded from the Master Register to the Slave Register
on the rising edge of LATCH. If EDGE/LEVEL = 0, data is loaded from the Master to the Slave Register while LATCH = 0. In
parallel mode, commands 1011 through 1110 execute asynchronously, on the WR rising edge, regardless of the state of LATCH
or EDGE/LEVEL. Parallel mode command 1111 executes a software “Latch” (see Table 1).
Chip Enable. When CE = 0 and CE = 1, the WR line is enabled.
Chip Enable. When CE = 0 and CE = 1, the WR line is enabled.
Analog Video Outputs.
Analog Ground.
D3
Parallel Data Bit Input D3 when SER/PAR = 0. D3 is unused with serial programming.
D2
Parallel Data Bit Input D2 when SER/PAR = 0. D2 is unused with serial programming.
3
FN4153.5
August 14, 2006