CD4015BT Datasheet, PDF (3/3 Pages) Intersil Corporation – CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

CD4015BT
Die Characteristics
DIE DIMENSIONS:
(2032µm x 2489µm x 533µm ±25.4µm)
80 x 98 x 21mils ±1mil
METALLIZATION:
Type: Al
Thickness: 12.5kÅ ±1.5kÅ
SUBSTRATE POTENTIAL:
Leave Floating or Tie to V_DD; Bond Pad #16 (V_DD) First
BACKSIDE FINISH:
Silicon
PASSIVATION:
Type: Phosphorus Doped Silox (S_iO₂)
Thickness: 13kÅ ±2.6kÅ
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm²
TRANSISTOR COUNT:
60
PROCESS:
Bulk CMOS
Metallization Mask Layout
CD4015BT
80mils
1
3
2
16
15
14
4
5
98mils
13
12
6
7
89
10
11
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