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CD4015BT Datasheet, PDF (1/3 Pages) Intersil Corporation – CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output | |||
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Data Sheet
CD4015BT
July 1999 File Number 4621.1
CMOS Dual 4-Stage Static Shift Register
With Serial Input/Parallel Output
Intersilâs Satellite Applications FlowTM (SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard ï¬ow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
CD4015BT consists of two identical, independent, 4-stage
serial-input/parallel output registers. Each register has
independent CLOCK and RESET inputs as well as a single
serial DATA input. âQâ outputs are available from each of the
four stages on both registers. All register stages are D type,
master-slave ï¬ip-ï¬ops. The logic level present at the DATA
input is transferred into the ï¬rst register stage and shifted
over one stage at each positive-going clock transition.
Resetting of all stages is accomplished by a high level on the
reset line. Register expansion to 8 stages using one
CD4015BT, or to more than 8 stages using additional
CD4015BTâs is possible.
Speciï¬cations
Speciï¬cations for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Speciï¬cations for the CD4015BT are
contained in SMD 5962-96624. A âhot-linkâ is provided from
our website for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
Intersilâs Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/quality/manuals.asp
Ordering Information
ORDERING
NUMBER
PART
NUMBER
TEMP.
RANGE
(oC)
5962R9662401TEC
CD4015BDTR
-55 to 125
5962R9662401TXC
CD4015BKTR
-55 to 125
NOTE: Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
Features
⢠QML Class T, Per MIL-PRF-38535
⢠Radiation Performance
- Gamma Dose (γ) 1 x 105 RAD(Si)
- SEP Effective LET > 75 MEV/gm/cm2
⢠Medium Speed Operation 12MHz (typ.) Clock Rate at VDD
- VSS = 10V
⢠Fully Static Operation
⢠8 Master-Slave Flip-Flops Plus Input and Output Buffering
⢠100% Tested For Quiescent Current at 20V
⢠5V, 10V and 15V Parametric Ratings
⢠Standardized Symmetrical Output Characteristics
Pinouts
CD4015BT (SBDIP), CDIP2-T16
TOP VIEW
CLOCK B 1
Q4B 2
Q3A 3
Q2A 4
Q1A 5
RESET A 6
DATA A 7
VSS 8
16 VDD
15 DATA B
14 RESET B
13 Q1B
12 Q2B
11 Q3B
10 Q4A
9 CLOCK A
CLOCK B
Q4B
Q3A
Q2A
Q1A
RESET A
DATA A
VSS
CD4015BT (FLATPACK), CDFP4-F16
TOP VIEW
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VDD
DATA B
RESET B
Q1B
Q2B
Q3B
Q4A
CLOCK A
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
Satellite Applications Flow⢠(SAF) is a trademark of Intersil Corporation.
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