HFA3824A Datasheet, PDF (29/40 Pages) Intersil Corporation – Direct Sequence Spread Spectrum Baseband Processor

Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4-0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
HFA3824A
CONFIGURATION REGISTER 7 ADDRESS (1Ch) MODEM STATUS REGISTER A (Continued)
This status bit indicates the status of the ANT_SEL pin.
Logic 0: Antenna A is selected.
Logic 1: Antenna B is selected.
This status bit indicates the present state of clear channel assessment (CCA) which is output pin 32. The CCA is being as-
serted as a result of a channel energy monitoring algorithm that is a function of RSSI, carrier sense, and time out counters
that monitor the channel activity.
This status bit, when active indicates Carrier Sense, or PN lock.
Logic 1: Carrier present.
Logic 0: No Carrier Sense.
This status bit indicates whether the RSSI signal is above or below the programmed RSSI 6-bit threshold setting. This signal
is referred as Energy Detect (ED).
Logic 1: RSSI is above the programmed threshold setting.
Logic 0: RSSI is below the programmed threshold setting.
This bit indicates the status of the output control pin MD_RDY (pin 34). It signals that a valid Preamble/Header has been
received and that the next available bit on the RXD bus will be the first data packet bit.
Logic 1: Envelopes the data packet as it becomes available on pin 35 (RXD).
Logic 0: No data packet on RXD serial bus.
This status bit indicates whether the external device has acknowledged that the channel is clear for transmission. This is the
same as the input signal TX_PE on pin 2.
Logic 1 = Acknowledgment that channel is clear to transmit.
Logic 0 = Channel is NOT clear to transmit.
This status bit indicates that a valid CRC16 has been calculated. The CRC16 is calculated on the Header information. The
CRC16 does not cover the preamble bits. This bit is valid even if checking was turned off via bit 5 of CR2.
Logic 1 = Valid CRC16 check.
Logic 0 = Invalid CRC16 check.
CONFIGURATION REGISTER 8 ADDRESS (20h) MODEM STATUS REGISTER B
This status bit indicates if the received signal field matched the contents of either CR42 or 43. This bit is valid even if checking
was turned off via bit 5 of CR2. Failure of signal field to match does not reset processor under any conditions.
Logic 1 = Signal field matched.
Logic 0 = Signal field did not match.
This bit is used to indicate the status of the SFD search timer. The device monitors the incoming Header for the SFD. If the
timer, times out the HFA3824A returns to its signal acquisition mode looking to detect the next Preamble and Header.
Logic 1 = SFD not found, return to signal acquisition mode.
Logic 0 = No time out during SFD search.
This status bit is used to indicate the modulation type for the data packet. This signal is generated by the header detection
circuitry in the receive interface.
Logic 0 = DBPSK.
Logic 1 = DQPSK.
ADcal (4:0)
CONFIGURATION REGISTER 9 ADDRESS (24h) I/O DEFINITION REGISTER
This register is used to define the phase of clocks and other interface signals.
This controls the phase of the RX_CLK output
Logic 1 = Invert clk
Logic 0 = Non-inverted clk
This control bit selects the active level of the MD_RDY output pin 34.
Logic 1 = MD_RDY is active 0.
Logic 0 = MD_RDY is active 1.
This control bit selects the active level of the Clear Channel Assessment (CCA) output pin 32.
Logic 1 = CCA active 1.
Logic 0 = CCA active 0.
This control bit selects the active level of the Energy Detect (ED) output which is an output pin at the test port, pin 45.
Logic 1 = ED active 0.
Logic 0 = ED active 1.
This control bit selects the active level of the Carrier Sense (CRS) output pin which is an output pin at the test port, pin 46.
Logic 1 = CRS active 0.
Logic 0 = CRS active 1.
2-127