LP3907 Datasheet, PDF (27/44 Pages) National Semiconductor (TI) – Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface

I²C Compatible Serial Interface
I²C SIGNALS
The LP3907 features an I²C compatible serial interface, using
two dedicated pins: SCL and SDA for I²C clock and data re-
spectively. Both signals need a pull-up resistor according to
the I²C specification. The LP3907 interface is an I²C slave that
is clocked by the incoming SCL clock.
Signal timing specifications are according to the I²C bus spec-
ification. The maximum bit rate is 400kbit/s. See I²C specifi-
cation from Philips for further details.
I²C DATA VALIDITY
The data on the SDA line must be stable during the HIGH
period of the clock signal (SCL), e.g.- the state of the data line
can only be changed when CLK is LOW.
I²C Signals: Data Validity
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I²C START AND STOP CONDITIONS
to HIGH while the SCL is HIGH. The ²C master always gen-
erates START and STOP bits. The I2C bus is considered to
START and STOP bits classify the beginning and the end of
be busy after START condition and free after STOP condition.
the I²C session. START condition is defined as the SDA signal
During data transmission, I²C master can generate repeated
transitioning from HIGH to LOW while the SCL line is HIGH.
START conditions. First START and repeated START condi-
STOP condition is defined as the SDA transitioning from LOW
tions are equivalent, function-wise.
START and STOP Conditions
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