ISLA112P25M Datasheet, PDF (27/29 Pages) Intersil Corporation – Power Amplifier Linearization

ISLA112P25M
Equivalent Circuits (Continued)
OVDD
2mA OR
3mA
DATA
DATA
OVDD
OVDD
D[11:0]P
D[11:0]N
OVDD
OVDD
DATA
2mA OR
3mA
DATA
DATA
D[11:0]
FIGURE 45. LVDS OUTPUTS
FIGURE 46. CMOS OUTPUTS
AVDD
+
0.535V
–
VCM
FIGURE 47. VCM_OUT OUTPUT
ADC Evaluation Platform
Intersil offers an ADC Evaluation platform which can be
used to evaluate the KADxxxxx ADC family. The platform
consists of a FPGA based data capture motherboard and
a family of ADC daughter cards. This USB based platform
allows a user to quickly evaluate the functioning of the
ISLA112P25MREP at room temperature with the
KAD5512P-25Q72 based daughter card at a user’s
specific application frequency requirements. More
information is available at:
http://www.intersil.com/converters/adc_eval_platform/
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies
require extra care in PC board layout. Many complex
board designs benefit from isolating the analog and
digital sections. Analog supply and ground planes should
be laid out under signal and clock inputs. Locate the
digital planes under outputs and logic pins. Grounds
should be joined under the chip.
Clock Input Considerations
Use matched transmission lines to the transformer inputs
for the analog input and clock signals. Locate
transformers and terminations as close to the chip as
possible.
Exposed Paddle
The exposed paddle must be electrically connected to
analog ground (AVSS) and should be connected to a
large copper plane using numerous vias for optimal
thermal performance.
Bypass and Filtering
Bulk capacitors should have low equivalent series
resistance. Tantalum is a good choice. For best
performance, keep ceramic bypass capacitors very close
to device pins. Longer traces will increase inductance,
resulting in diminished dynamic performance and
accuracy. Make sure that connections to ground are
direct and low impedance. Avoid forming ground loops.
LVDS Outputs
Output traces and connections must be designed for 50Ω
(100Ω differential) characteristic impedance. Keep traces
27
FN7646.1
November 17, 2011