ISLA112P25M Datasheet, PDF (15/29 Pages) Intersil Corporation – Power Amplifier Linearization

ISLA112P25M
CLKN
CLKP
RESETN
ORP
CLKOUTP
CALIBRATION TIME
CALIBRATION BEGINS
CALIBRATION COMPLETE
FIGURE 22. CALIBRATION TIMING
User-Initiated Reset
Recalibration of the ADC can be initiated at any time by
driving the RESETN pin low for a minimum of one clock
cycle. An open-drain driver with a drive strength of less
than 0.5mA is recommended, RESETN has an internal
high impedance pull-up to OVDD. As is the case during
power-on reset, the SDO, RESETN and DNC pins must be
in the proper state for the calibration to successfully
execute.
The performance of the ISLA112P25MREP changes with
variations in temperature, supply voltage or sample rate.
The extent of these changes may necessitate
recalibration, depending on system performance
requirements. Best performance will be achieved by
recalibrating the ADC under the environmental conditions
at which it will operate. Note: To ensure device accuracy
the measurement temperature is to be within 60°C of
the calibration temperature.
A supply voltage variation of less than 100mV will
generally result in an SNR change of less than 0.5dBFS
and SFDR change of less than 3dBc.
In situations where the sample rate is not constant, best
results will be obtained if the device is calibrated at the
highest sample rate. Reducing the sample rate by less
than 75MSPS will typically result in an SNR change of
less than 0.5dBFS and an SFDR change of less than
3dBc.
Figures 23 and 24 show the effect of temperature on
SNR and SFDR performance without recalibration. In
each plot, the ADC is calibrated at +25°C and
temperature is varied over the operating range without
recalibrating. The average change in SNR/SFDR is
shown, relative to the +25°C value.
70
69
68
67
1.7V
66
65
64
63
1.8V
62
1.9V
61
60
-55 -35 -15
5 25 45 65 85 105 125
TEMPERATURE (°C)
FIGURE 23. SNR PERFORMANCE vs TEMPERATURE
(CAL DONE AT +25°C)
90
1.7V
85
1.8V
80
75
1.9V
70
65
60
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE (°C)
FIGURE 24. SFDR PERFORMANCE vs TEMPERATURE
(CAL DONE AT +25°C)
Analog Input
The ADC core contains a fully differential input
(VINP/VINN) to the sample and hold amplifier (SHA). The
ideal full-scale input voltage is 1.45V, centered at the
VCM voltage of 0.535V as shown in Figure 25.
Best performance is obtained when the analog inputs are
driven differentially. The common-mode output voltage,
VCM, should be used to properly bias the inputs as
shown in Figures 26 through 28. An RF transformer will
give the best noise and distortion performance for
wideband and/or high intermediate frequency (IF)
inputs. Two different transformer input schemes are
shown in Figures 26 and 27.
15
FN7646.1
November 17, 2011