KAD5512P Datasheet, PDF (26/36 Pages) List of Unclassifed Manufacturers – Low Power 12-Bit, 250/210/170/125MSPS ADC

KAD5512P
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By
default, the tri-level NAPSLP pin can select normal
operation or sleep modes (refer to “Nap/Sleep” on
page 21). This functionality can be overridden and
controlled through the SPI. This is an indexed function
when controlled from the SPI, but a global function when
driven from the pin. This register is not changed by a
Soft Reset.
TABLE 10. POWER-DOWN CONTROL
VALUE
0x25[2:0]
POWER-DOWN MODE
000
Pin Control
001
Normal Operation
010
Nap Mode
100
Sleep Mode
Nap mode must be entered by executing the following
sequence:
SEQUENCE
1
2
3
4
REGISTER
0x10
0x25
0x10
0x25
VALUE
0x01
0x02
0x02
0x02
Return to Normal operation as follows:
SEQUENCE
1
2
3
4
REGISTER
0x10
0x25
0x10
0x25
VALUE
0x01
0x01
0x02
0x01
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP
When using the clock divider, it’s not possible to
determine the synchronization of the incoming and
divided clock phases. This is particularly important when
multiple ADCs are used in a time-interleaved system.
The phase slip feature allows the rising edge of the
divided clock to be advanced by one input clock cycle
when in CLK/4 mode, as shown in Figure 41. Execution
of a phase_slip command is accomplished by first writing
a ‘0’ to bit 0 at address 71h followed by writing a ‘1’ to bit
0 at address 71h (32 sclk cycles).
CLK
CLK÷4
CLK÷4
SLIP ONCE
CLK = CLKP – CLKN
1.00ns
4.00ns
CLK÷4
SLIP TWICE
FIGURE 41. PHASE SLIP: CLK÷4 MODE, f_CLOCK =
1000MHz
ADDRESS 0X72: CLOCK_DIVIDE
The KAD5512P has a selectable clock divider that can be
set to divide by four, two or one (no division). By default,
the tri-level CLKDIV pin selects the divisor (refer to “VCM
Output” on page 20). This functionality can be
overridden and controlled through the SPI, as shown in
Table 11. This register is not changed by a Soft Reset.
TABLE 11. CLOCK DIVIDER SELECTION
VALUE
0x72[2:0]
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
010
Divide by 2
100
Divide by 4
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
KAD5512P can present output data in two physical
formats: LVDS or LVCMOS. Additionally, the drive
strength in LVDS mode can be set high (3mA) or low
(2mA). By default, the tri-level OUTMODE pin selects the
mode and drive level (refer to “Digital Outputs” on
page 21). This functionality can be overridden and
controlled through the SPI, as shown in Table 12.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to “Data
Format” on page 22). This functionality can be overridden
and controlled through the SPI, as shown in Table 13.
This register is not changed by a Soft Reset.
TABLE 12. OUTPUT MODE CONTROL
VALUE
000
001
010
100
0x93[7:5]
Pin Control
LVDS 2mA
LVDS 3mA
LVCMOS
26
FN6807.4
October 1, 2010