ISL62881C Datasheet, PDF (26/37 Pages) Intersil Corporation – Single-Phase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs

ISL62881C, ISL62881D
NAME
VSEN
RTN
VDD
IMON
ISUM-
ISUM+
TABLE 5. LAYOUT CONSIDERATIONS (Continued)
LAYOUT CONSIDERATION
Place the VSEN/RTN filter (C12, C13) in close proximity of the controller for good decoupling.
A capacitor (C16) decouples it to GND. Place it in close proximity of the controller.
Place the filter capacitor (C21) close to the CPU.
Place the current sensing circuit in general proximity of the controller.
Place C82 very close to the controller.
Place NTC thermistors R₄₂ next to inductor (L1) so it senses the inductor temperature correctly.
The power stage sends a pair of VSUM+ and VSUM- signals to the controller. Run these two signal traces in parallel
fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads.
Route R₆₃ to the phase-node side pad of inductor L1. Route the other current sensing trace to the output side pad
of inductor L1.
If possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to
the center of the pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of
the inductor. The following drawings show the two preferred ways of routing current sensing traces.
INDUCTOR
INDUCTOR
VIAS
CURRENT-
CURRENT-
SENSING TRACES SENSING TRACES
VIN A capacitor (C17) decouples it to GND. Place it in close proximity of the controller.
BOOT Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
UGATE
PHASE
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing PHASE trace to the high-side MOSFET (Q2 and Q8) source pins
instead of general phase node copper.
VSSP Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
LGATE
or
crossing over or getting close. Recommend routing VSSP to the low-side MOSFET (Q3 and Q9) source pins instead
of general power ground plane for better performance.
LGATEa and
LGATEb
VCCP A capacitor (C22) decouples it to GND. Place it in close proximity of the controller.
VID0~6 No special consideration.
VR_ON No special consideration.
DPRSLPVR No special consideration.
Phase Node Minimize phase node copper area. Don’t let the phase node copper overlap with/getting close to other sensitive
traces. Cut the power ground plane to avoid overlapping with phase node copper.
Minimize the loop consisting of input capacitor, high-side MOSFETs and low-side MOSFETs (e.g.: C27, C33, Q2, Q8,
Q3 and Q9).
26
FN7596.0
March 8, 2010