ISL12022MA_10 Datasheet, PDF (26/29 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving

ISL12022MA
SIGNALS ^S
S
FROM THE ^T IDENTIFICATION
T _{IDENTIFICATION}
S
MASTER ^A
BYTE WITH
ADDRESS
A _{BYTE WITH}
A
A
T
R
R/W = 0
T
BYTE
R
R/W = 1
T
C
C
O
K
K
P
SIGNAL AT
SDA
11011110
A
SIGNALS FROM
C
THE SLAVE
K
11011111
A
A
C
C _{FIRST READ}
K
K _{DATA BYTE}
FIGURE 19. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
LAST READ
DATA BYTE
Following the Slave Byte is a one byte word address. The
word address is either supplied by the master device or
obtained from an internal counter. On power-up, the
internal address counter is set to address 00h, so a
current address read starts at address 00h. When
required, as part of a random read, the master must
supply the 1 Word Address Bytes, as shown in Figure 19.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in the
“read” section. For a random read of the Control/Status
Registers, the slave byte must be “1101111x” in both
places.
Write Operation
A Write operation requires a START condition, followed by
a valid Identification Byte, a valid Address Byte, a Data
Byte, and a STOP condition. After each of the three
bytes, the ISL12022MA responds with an ACK. At this
time, the I²C interface enters a standby state.
Read Operation
A Read operation consists of a three byte instruction,
followed by one or more Data Bytes (see Figure 19).
The master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W
bit set to “0”, an Address Byte, a second START, and a
second Identification byte with the R/W bit set to “1”.
After each of the three bytes, the ISL12022MA responds
with an ACK. Then the ISL12022MA transmits Data
Bytes as long as the master responds with an ACK
during the SCL cycle following the eighth bit of each
byte. The master terminates the read operation (issuing
a STOP condition) following the last bit of the last Data
Byte (see Figure 19).
The Data Bytes are from the memory location indicated
by an internal pointer. This pointer’s initial value is
determined by the Address Byte in the Read operation
instruction, and increments by one during transmission
of each Data Byte. After reaching the memory location
2Fh, the pointer “rolls over” to 00h, and the device
continues to output data for each ACK received.
Application Section
Battery Backup Details
The ISL12022MA has automatic switchover to battery
backup when the V_DD drops below the V_BAT mode
threshold. A wide variety of backup sources can be used,
including standard and rechargeable lithium,
supercapacitors, or regulated secondary sources. The
serial interface is disabled in battery backup, while the
oscillator and RTC registers are operational. The SRAM
register contents are powered to preserve their contents
as well.
The input voltage range for V_BAT is 1.8V to 5.5V, but keep
in mind the temperature compensation only operates for
V_BAT > 2.7V. Note that the device is not guaranteed to
operate with a V_BAT < 1.8V, so the battery should be
changed before discharging to that level. It is strongly
advised to monitor the low battery indicators in the status
registers and take action to replace discharged batteries.
If a supercapacitor is used, it is possible that it may
discharge to below 1.8V during prolonged power-down.
Once powered up, the device may lose serial bus
communications until both V_DD and V_BAT are powered
down together. To avoid that situation, including
situations where a battery may discharge deeply, the
circuit in Figure 20 can be used.
V_DD = 2.7V
TO 5.5V
C_IN
0.1µF
ISL12022MA
VDD VBAT
GND
J_BAT
C_BAT
0.1µF
D_BAT
BAT43W
+V^{BAT = 1.8V}
TO 3.2V
FIGURE 20. SUGGESTED BATTERY BACKUP CIRCUIT
The diode, D_BAT will add a small drop to the battery
voltage but will protect the circuit should battery voltage
drop below 1.8V. The jumper is added as a safeguard
should the battery ever need to be disconnected from the
circuit.
The V_DD negative slew rate should be limited to below
the data sheet spec (10V/ms) otherwise battery
switchover can be delayed, resulting in SRAM contents
corruption and oscillator operation interruption.
26
FN7575.1
July 9, 2010