ISL12022MA_10 Datasheet, PDF (20/29 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving

ISL12022MA
BETA VALUES = (AT(max) - AT (min))/63, where:
AT(max) = F_OUT in ppm (at AT = 00H) and
AT(min) = F_OUT in ppm (at AT = 3FH).
The BETA VALUES result is indexed in the right hand
column and the resulting Beta factor (for the register) is
in the same row in the left column.
The ISL12022MA has a preset BETA value corresponding
to the crystal in the module. This value is recalled on
initial power-up and is preset in device production.
It is READ ONLY and cannot be overwritten by the
user.
TABLE 16. BETA VALUES
BETA<4:0>
01000
00111
00110
00101
00100
00011
00010
00001
00000
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
AT STEP ADJUSTMENT
0.5000
0.5625
0.6250
0.6875
0.7500
0.8125
0.8750
0.9375
1.0000
1.0625
1.1250
1.1875
1.2500
1.3125
1.3750
1.4375
1.5000
1.5625
1.6250
1.6875
1.7500
1.8125
1.8750
1.9375
2.0000
Final Analog Trimming Register (FATR)
This register shows the final setting of AT after
temperature correction. It is read-only; the user cannot
overwrite a value to this register. This value is accessible
as a means of monitoring the temperature compensation
function. See Table 17 and Table 18 (for values).
TABLE 17. FINAL ANALOG TRIMMING REGISTER
ADDR 7 6 5
4
3
2
1
0
0Eh 0 0 FATR5 FATR4 FATR3 FATR2 FATR1 FATR0
Final Digital Trimming Register (FDTR)
This Register shows the final setting of DT after
temperature correction. It is read-only; the user cannot
overwrite a value to this register. The value is accessible
as a means of monitoring the temperature compensation
function. The corresponding clock adjustment values are
shown in Table 19. The FDTR setting has both positive
and negative settings to adjust for any offset in the
crystal.
.
TABLE 18. FINAL DIGITAL TRIMMING REGISTER
ADDR 7 6 5
4
3
2
1
0
0Fh 0 0 0 FDTR4 FDTR3 FDTR2 FDTR1 FDTR0
TABLE 19. CLOCK ADJUSTMENT VALUES FOR FINAL
DIGITAL TRIMMING REGISTER
FDTR<2:0>
DECIMAL
ppm
ADJUSTMENT
00000
0
0
00001
1
30.5
00010
2
61
00011
3
91.5
00100
4
122
00101
5
152.5
00110
6
183
00111
7
213.5
01000
8
244
01001
9
274.5
01010
10
305
10000
0
0
10001
-1
-30.5
10010
-2
-61
10011
-3
-91.5
10100
-4
-122
10101
-5
-152.5
10110
-6
-183
10111
-7
-213.5
11000
-8
-244
11001
-9
-274.5
11010
-10
-305
ALARM Registers (10h to 15h)
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte
functions as an enable bit (enable = “1”). These enable
bits specify which alarm registers (seconds, minutes,
etc.) are used to make the comparison. Note that there
is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match
occurs between the alarm registers and the RTC
20
FN7575.1
July 9, 2010