X98027 Datasheet, PDF (25/29 Pages) Xicor Inc. – PRELIMINARY INFORMATION

X98027
TABLE 8. X98027 CRYSTAL COMPENSATION
CRYSTAL
FREQUENCY
RANGE (MHz)
REGISTER 0x2B VALUE
VALUE
(DECIMAL)
HEX
23 - 23.9
24
0x18
23.9 - 25
23
0x17
25.0 - 26.2
22
0x16
26.2 - 27
21
0x15
HSYNC_IN
Conditions required: negative polarity VSYNC, with no serrations, and t₁ = t₂
t₁
t₂
FIGURE 11. CSYNC ON HSYNC THAT MAY CAUSE SPORADIC IMAGE SHIFTS
Internal Voltage Regulator The X98027 features a 3.3V to
1.9V voltage regulator (pins 64 and 65). This regulator
typically sources up to 100mA at 1.9V, dissipating up to
140mW in heat. Providing an external, clean 1.8V supply to
the VCORE, VPLL, and VCOREADC will substantially
reduce power dissipation
• Buffering Digital Outputs Switching 48 DATA OUTPUT
bits at a 275MHz/2 rate consumes a lot of current. The
higher the capacitance on the external databus, the higher
the switching current. To minimize current consumption
inside the X98027, data buffers such as the
SN64AVC16827 should be placed between the X98027’s
data outputs and the external databus. For bus
capacitances of 15pF or lower, this is highly
recommended. For bus capacitances greater than
15pF, this is mandatory!
Reset
The X98027 has a Power-On Reset (POR) function that
resets the chip to its default state when power is initially
applied, including resetting all the registers to their default
settings as described in the Register Listing. The external
RESET pin duplicates the reset function of the POR without
having to cycle the power supplies. The RESET pin does not
need to be used in normal operation and can be tied high.
Rare CSYNC Considerations
Intersil has discovered one anomaly in its sync separator
function. If the CSYNC signal shown in Figure 11 is present
on the HSYNC input, and the sync source is set to CSYNC
on HSYNC, HS_OUT may sporadically lock to the wrong edge
of HSYNC_IN. This will cause the HS_OUT to have the wrong
position relative to pixel 0, resulting in the image shifting left
or right by the width of the HSYNC_IN signal for about 1
second before it corrects itself.
This only happens with the exact waveshape shown in
Figure 11. If the polarity of the sync signal is inverted from
that shown in Figure 11, the problem will not occur. If there
are any serrations during the VSYNC period, the problem
will not occur. The problem also will not occur if the sync
signal is on the SOG input.
This is a rarely used composite sync format; in most
applications it will never be encountered. However if this
CSYNC waveform must be supported, there is a simple
applications solution using an XOR gate.
The output of the XOR gate is connected to the HSYNC_IN
input of the X98027. One of the XOR inputs is connected to
the HSYNC/CSYNC source, and the other input is
connected to a general purpose I/O. For all sync sources
except the CSYNC shown in Figure 11, the input connected
to the GPIO should be driven low.
If the system microcontroller detects a mode corresponding
to the sync type and polarity shown in Figure 11, it should
drive the GPIO pin high. This will invert the CSYNC signal
seen by the X98027 and prevent any spontaneous image
shifting.
X98027 Serial Communication
Overview
The X98027 uses a 2 wire serial bus for communication with
its host. SCL is the Serial Clock line, driven by the host, and
SDA is the Serial Data line, which can be driven by all
devices on the bus. SDA is open drain to allow multiple
devices to share the same bus simultaneously.
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FN8221.0
May 26, 2005