X98027 Datasheet, PDF (24/29 Pages) Xicor Inc. – PRELIMINARY INFORMATION

X98027
HSYNC_IN
(to A and B)
DPLL Lock Edge
Analog Video In
(to A and B)
P_N-3 P_N-2 P_N-1 P_N P₀ P₁ P₂ P₃ P₄ P₅ P₆ P₇ P₈ P₉ P₁₀ P₁₁ P₁₂
PIXELCLK (A)
(Internal)
DATACLK (A)
DATA_PRI (A)
DATA_SEC (A)
HS_OUT (A)
PIXELCLK (B)
(Internal)
DATACLK (B)
D_N-3
D₀
D_N-1
D₂
CLKINV_IN (A) = GND_D
½ PIXELCLK = ¼ DATACLK Delay
DATA_PRI (B)
D_N-2
D₁
DATA_SEC (B)
D_N
D₃
HS_OUT (B)
CLKINV_IN (B) = GND_D
FIGURE 10. ALTERNATE PIXEL SAMPLING (48 BIT MODE)
._{Initialization}
The X98027 initializes with default register settings for an
AC-coupled, RGB input on the VGA1 channel, with a 24 bit
output.
The following registers should be written to fully enable the
chip:
• Register 0x1C should be set to 0x49 to improve DPLL
performance in video modes
• Register 0x23 should be set to 0x78 to enable the DC
Restore function
• Write the correct crystal compensation value to Register
0x2B (see below).
Power Dissipation at QXGA Speeds
Because of the very high speed of the X98027, power
consumption is a concern. There are several things that can
be done to reduce power consumption:
Internal Clock Frequency The internal clock frequencies
need to be tightly controlled to minimize power consumption.
Register 0x2B should be set to 1 + the integer portion of
(2*fPIXELCLOCKMAX/fCRYSTAL). For example, if the
maximum pixel clock is 263MHz, and the crystal frequency is
24MHz, then register 0x2B should be set to 1 +
INT(2*263/24) = 1 + INT(21.917) = 1 + 21 = 22 = 0x16. The
following table illustrates the compensation values required
to operate the X98027 at its maximum speed of 275MHz. If
lower maximum Pixel Clock frequencies are needed, using
the formula above will minimize power consumption.
24
FN8221.0
May 26, 2005