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ISL3332 Datasheet, PDF (25/26 Pages) Intersil Corporation – 3.3V, ±15kV ESD Protected, Two Port, Dua Protocol RS-232/RS-485 Transceivers
ISL3332, ISL3333
Shrink Small Outline Plastic Packages (SSOP)
N
INDEX
AREA
H
E
-B-
0.25(0.010) M B M
GAUGE
PLANE
123
-A-
D
SEATING PLANE
A
L
0.25
0.010
-C-
α
e
A1
A2
C
B
0.10(0.004)
0.25(0.010) M C A M B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess of
“B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M28.209 (JEDEC MO-150-AH ISSUE B)
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN
MAX
MIN
MAX NOTES
A
-
0.078
-
2.00
-
A1
0.002
-
0.05
-
-
A2
0.065 0.072
1.65
1.85
-
B
0.009 0.014
0.22
0.38
9
C
0.004 0.009
0.09
0.25
-
D
0.390 0.413
9.90 10.50
3
E
0.197 0.220
5.00
5.60
4
e
0.026 BSC
0.65 BSC
-
H
0.292 0.322
7.40
8.20
-
L
0.022 0.037
0.55
0.95
6
N
28
28
7
α
0°
8°
0°
8°
-
Rev. 2 6/05
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
25
FN6362.0
May 27, 2008