HSP50214 Datasheet, PDF (25/54 Pages) Intersil Corporation – Programmable Downconverter

HSP50214
LOOP
FILTER
µP
TIMING
NCO
ACC.
CLKIN/R_T
NCO DIVIDE = 4N†
PROGRAMMABLE
DIVIDER
(NCO DIVIDE)/2†
-
12
+
4
TE(15:0)
REFERENCE
DIVIDE = N †
EN
T_X DATA CLK
(REFCLK)
PROGRAMMABLE
DIVIDER
TO T_X BLOCK
(MODULATOR)
R_T = TOTAL DECIMATION (CIC, HB FILTERS AND FIR)
† Controlled via microprocessor interface.
FIGURE 27A. TIMING ERROR APPLICATION
TABLE 11. MAG/PHASE BIT WEIGHTING
BIT
MAGNITUDE
PHASE (^o)
15 (MSB)
2² Always 0
180
14
2¹
90
13
2⁰
45
12
2^-1
22.5
11
2^-2
11.25
10
2^-3
5.625
9
2^-4
2.8125
8
2^-5
1.40625
7
2^-6
0.703125
6
2^-7
0.3515625
5
2^-8
0.17578125
4
2^-9
0.087890625
3
2^-10
0.043945312
2
2^-11
0.021972656
1
2^-12
0.010986328
0 (LSB)
2^-13
0.005483164
Cartesian to Polar Converter
The Cartesian to Polar converter computes the magnitude
and phase of the I/Q vector inputs. The I and Q inputs are
16 bits. The converter phase output is 18 bits (truncated)
with the 16 MSB’s routed to the output formatter and all 18
bits routed to the frequency discriminator. The 16-bit output
phase can be interpreted either as two’s complement (-0.5 to
approximately 0.5) or unsigned (0.0 to approximately 1.0),
as shown in Figure 28. The phase conversion gain is 1/2π.
The phase resolution is 16 bits. The 16-bit magnitude is
unsigned binary format with a range from 0 to 2.32. The
magnitude conversion gain is 1.64676. The magnitude reso-
lution is 16 bits. The MSB is always zero.
Table 11 details the phase and magnitude weighting for the
16 bits output from the PDC.
7fff
±π
8000
+π/2
4000 3ff f
Q
I ⁰⁰⁰⁰
0
ffff
7fff
π
8000
π/2
4000 3fff
Q
I ⁰⁰⁰⁰
0
ffff
bfff c000
-π/2
bfff c000
3π/2
FIGURE 28. PHASE BIT MAPPING OF COORDINATE
CONVERTER OUTPUT
The magnitude and phase computation requires 17 clocks
for full precision. At the end of the 17 clocks, the magnitude
and phase are latched into a register to be held for the next
stage, either the Output Formatter or frequency discrimina-
tor. If a new input sample arrives before the end of the 17
cycles, the results of the computations up until that time, are
latched. This latching means that an increase in speed
causes only a decrease in resolution. Table 12 details the
exact resolution that can be obtained with a fixed number of
clock cycles up to the required 17. The input magnitude and
phase errors induced by normal SNR values will almost
always be worse than the Cartesian to Polar conversion.
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